Jonas Paulsson 6239df0eb2 [SystemZ] Pass copy-hinted regs first from getRegAllocationHints(). ... When computing register allocation hints for a GRX32Bit register, make sure that any of the hinted registers that are also copy hints are returned first in the list. Review: Ulrich Weigand. llvm-svn: 349037		2018-12-13 14:37:05 +00:00
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addr-01.ll
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branch-folder-hoist-livein.mir
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builtins.ll
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clear-liverange-spillreg.mir
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codegenprepare-splitstore.ll
codemodel.ll	[Targets] Fixup incorrect targets in codemodel tests	2018-12-10 20:55:34 +00:00
combine_loads_from_build_pair.ll
cond-load-01.ll
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cond-move-01.ll
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cond-move-04.mir
cond-move-05.mir
cond-move-regalloc-hints.mir	[SystemZ] Pass copy-hinted regs first from getRegAllocationHints().	2018-12-13 14:37:05 +00:00
cond-store-01.ll
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DAGCombine_trunc_extract.ll
DAGCombiner_illegal_BUILD_VECTOR.ll
DAGCombiner_isAlias.ll
dyn-alloca-offset.ll
expand-zext-pseudo.ll
extract-vector-elt-zEC12.ll
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fp-cmp-01.ll
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fp-cmp-07.mir
fp-const-01.ll
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fp-conv-05.ll
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fp-conv-07.ll
fp-conv-08.ll
fp-conv-09.ll
fp-conv-10.ll	Regenerate FP_TO_INT tests.	2018-10-27 15:00:38 +00:00
fp-conv-11.ll
fp-conv-12.ll	Regenerate FP_TO_INT tests.	2018-10-27 15:00:38 +00:00
fp-conv-13.ll
fp-conv-14.ll
fp-conv-15.ll
fp-conv-16.ll
fp-conv-17.mir
fp-copysign-01.ll
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fp-libcall.ll
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fp-mul-01.ll
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fp-mul-10.ll
fp-mul-11.ll
fp-mul-12.ll
fp-neg-01.ll
fp-neg-02.ll
fp-round-01.ll	[SystemZ] Add a couple of missing tests	2018-11-09 19:16:21 +00:00
fp-round-02.ll
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fp-sincos-01.ll
fp-sqrt-01.ll
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fpc-intrinsics.ll
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frameaddr-01.ll
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int-mul-01.ll
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ipra-04.ll
ipra.ll
isel-debug.ll	[SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().	2018-10-26 00:02:33 +00:00
knownbits-intrinsics-binop.ll
knownbits-intrinsics-unpack.ll
knownbits.ll	Regenerate knownbits test. NFCI.	2018-12-12 13:21:03 +00:00
la-01.ll
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la-04.ll
list-ilp-crash.ll
lit.local.cfg
load-and-test.mir
locr-legal-regclass.ll
loop-01.ll
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loop-03.ll
loop-04.ll
lower-copy-undef-src.mir
mature-mc-support.ll
memchr-01.ll
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memcpy-01.ll
memcpy-02.ll
memset-01.ll
memset-02.ll
memset-03.ll
memset-04.ll
misched-readadvances.mir	[SchedModel] Fix for read advance cycles with implicit pseudo operands.	2018-10-30 15:04:40 +00:00
multiselect.ll
no-postra-sink.mir
or-01.ll
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or-03.ll
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or-08.ll
patchpoint-invoke.ll
patchpoint.ll
pie.ll
postra-sched-expandedops.mir
pr31710.ll
pr32372.ll
pr32505.ll
pr36164.ll	[DAGCombine] Improve alias analysis for chain of independent stores.	2018-11-08 19:14:20 +00:00
prefetch-01.ll
RAbasic-invalid-LR-update.mir
regalloc-fast-invalid-kill-flag.mir	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
regalloc-GR128-02.mir	[SystemZ] Bugfix in shouldCoalesce()	2018-11-08 15:29:48 +00:00
regalloc-GR128.ll
ret-addr-01.ll
risbg-01.ll
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risbg-03.ll
risbg-04.ll
rnsbg-01.ll
rosbg-01.ll
rosbg-02.ll	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
rot-01.ll
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rxsbg-01.ll
selectcc-01.ll
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signbits-intrinsics-binop.ll
signbits-intrinsics-unpack.ll
signbits.ll
spill-01.ll
splitMove_undefReg_mverifier_2.ll
splitMove_undefReg_mverifier.ll
stack-guard.ll
stack-size-section.ll
stackmap-nops.ll
stackmap-shadow-optimization.ll
stackmap.ll
store_nonbytesized_vecs.ll
strcmp-01.ll
strcmp-nobuiltin.ll
strcpy-01.ll
strcpy-nobuiltin.ll
strlen-01.ll
strlen-nobuiltin.ll
subregliveness-01.ll
subregliveness-02.ll
subregliveness-03.ll
subregliveness-04.ll	DAG combiner: fold (select, C, X, undef) -> X	2018-11-16 23:13:38 +00:00
subregliveness-05.ll	[SystemZ] make test immune to improvements in undef simplification	2018-11-18 16:50:44 +00:00
subregliveness-06.mir
subregliveness-07.mir
swift-return.ll
swifterror.ll
swiftself.ll
tail-call-mem-intrinsics.ll
tdc-01.ll
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tls-01.ll
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trap-01.ll
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twoaddr-sink.ll
unaligned-01.ll
undef-flag.ll
vec-abi-align.ll
vec-abs-01.ll
vec-abs-02.ll
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vec-add-01.ll
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vec-cmp-05.ll
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vec-cmp-07.ll
vec-cmp-cmp-logic-select.ll
vec-cmpsel.ll
vec-combine-01.ll
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vec-const-01.ll
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vec-const-14.ll
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vec-conv-01.ll
vec-conv-02.ll
vec-ctlz-01.ll
vec-ctpop-01.ll
vec-ctpop-02.ll
vec-cttz-01.ll
vec-div-01.ll
vec-div-02.ll
vec-extract-01.ll
vec-extract-02.ll
vec-intrinsics-01.ll
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vec-load-element.ll
vec-log-01.ll
vec-max-01.ll
vec-max-02.ll
vec-max-03.ll
vec-max-04.ll
vec-max-05.ll
vec-min-01.ll
vec-min-02.ll
vec-min-03.ll
vec-min-04.ll
vec-min-05.ll
vec-move-01.ll
vec-move-02.ll
vec-move-03.ll
vec-move-04.ll
vec-move-05.ll
vec-move-06.ll
vec-move-07.ll
vec-move-08.ll
vec-move-09.ll
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vec-move-13.ll
vec-move-14.ll
vec-move-15.ll
vec-move-16.ll
vec-move-17.ll
vec-move-18.ll
vec-move-19.ll	[SystemZ] Avoid inserting same value after replication	2018-11-09 15:44:28 +00:00
vec-move-20.ll	[SystemZ] Replicate the load with most uses in buildVector()	2018-11-12 08:12:20 +00:00
vec-move-21.ll	[SystemZ] Increase the number of VLREPs	2018-11-13 08:37:09 +00:00
vec-move-22.ll	[SystemZ] Increase the number of VLREPs	2018-11-13 08:37:09 +00:00
vec-mul-01.ll
vec-mul-02.ll
vec-mul-03.ll
vec-mul-04.ll
vec-mul-05.ll
vec-neg-01.ll
vec-neg-02.ll
vec-or-01.ll
vec-or-02.ll
vec-or-03.ll
vec-perm-01.ll
vec-perm-02.ll
vec-perm-03.ll
vec-perm-04.ll
vec-perm-05.ll
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vec-round-01.ll
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vec-sext.ll
vec-shift-01.ll
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vec-shift-07.ll
vec-sqrt-01.ll
vec-sqrt-02.ll
vec-sub-01.ll
vec-sub-02.ll
vec-trunc-to-i1.ll	[TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts	2018-12-12 13:43:07 +00:00
vec-xor-01.ll
vec-xor-02.ll
vec-zext.ll
vectorizer-output-3xi32.ll
xor-01.ll
xor-02.ll
xor-03.ll
xor-04.ll
xor-05.ll
xor-06.ll
xor-07.ll
xor-08.ll