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4b6f06420e
The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
133 lines
3.7 KiB
LLVM
133 lines
3.7 KiB
LLVM
; Test 16-bit atomic ORs.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
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; Check OR of a variable.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK.
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; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
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; before being used. This shift is independent of the other loop prologue
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; instructions.
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define i16 @f1(i16 *%src, i16 %b) {
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; CHECK-LABEL: f1:
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; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
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; CHECK-DAG: sll %r2, 3
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; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
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; CHECK: or [[ROT]], %r3
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
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; CHECK: jl [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 16(%r2)
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f1:
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; CHECK-SHIFT1: sll %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f1:
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; CHECK-SHIFT2: sll %r3, 16
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw or i16 *%src, i16 %b seq_cst
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ret i16 %res
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}
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; Check the minimum signed value. We OR the rotated word with 0x80000000.
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define i16 @f2(i16 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
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; CHECK-DAG: sll %r2, 3
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; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
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; CHECK: oilh [[ROT]], 32768
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
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; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
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; CHECK: jl [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 16(%r2)
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f2:
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; CHECK-SHIFT1: sll %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f2:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw or i16 *%src, i16 -32768 seq_cst
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ret i16 %res
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}
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; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfffe0000.
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define i16 @f3(i16 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: oilh [[ROT]], 65534
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f3:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f3:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw or i16 *%src, i16 -2 seq_cst
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ret i16 %res
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}
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; Check ORs of 1. We OR the rotated word with 0x00010000.
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define i16 @f4(i16 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: oilh [[ROT]], 1
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f4:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f4:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw or i16 *%src, i16 1 seq_cst
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ret i16 %res
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}
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; Check the maximum signed value. We OR the rotated word with 0x7fff0000.
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define i16 @f5(i16 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: oilh [[ROT]], 32767
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f5:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f5:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw or i16 *%src, i16 32767 seq_cst
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ret i16 %res
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}
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; Check ORs of a large unsigned value. We OR the rotated word with
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; 0xfffd0000.
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define i16 @f6(i16 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: oilh [[ROT]], 65533
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f6:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f6:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw or i16 *%src, i16 65533 seq_cst
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ret i16 %res
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}
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