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llvm-mirror/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

50 lines
1.4 KiB
YAML

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,VI %s
# RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,CI %s
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,SI %s
---
name: m0_sendmsg
body: |
; GCN-LABEL: name: m0_sendmsg
; GCN: $m0 = S_MOV_B32 -1
; VI-NEXT: S_NOP 0
; GFX9-NEXT: S_NOP 0
; GCN-NEXT: S_SENDMSG 3, implicit $exec, implicit $m0
bb.0:
$m0 = S_MOV_B32 -1
S_SENDMSG 3, implicit $exec, implicit $m0
S_ENDPGM
...
---
name: m0_sendmsghalt
body: |
; GCN-LABEL: name: m0_sendmsghalt
; GCN: $m0 = S_MOV_B32 -1
; VI-NEXT: S_NOP 0
; GFX9-NEXT: S_NOP 0
; GCN-NEXT: S_SENDMSGHALT 3, implicit $exec, implicit $m0
bb.0:
$m0 = S_MOV_B32 -1
S_SENDMSGHALT 3, implicit $exec, implicit $m0
S_ENDPGM
...
---
name: m0_ttracedata
body: |
; GCN-LABEL: name: m0_ttracedata
; GCN: $m0 = S_MOV_B32 -1
; VI-NEXT: S_NOP 0
; GFX9-NEXT: S_NOP 0
; GCN-NEXT: S_TTRACEDATA implicit $m0
bb.0:
$m0 = S_MOV_B32 -1
S_TTRACEDATA implicit $m0
S_ENDPGM
...