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AsmParser
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[MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex}
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2020-02-14 23:08:40 -08:00 |
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Disassembler
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[Hexagon] v67+ HVX register pairs should support either direction
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2020-02-14 12:43:43 -06:00 |
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MCTargetDesc
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[Hexagon][NFC] Rename VK_Hexagon_PCREL to VK_PCREL
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2020-02-19 09:52:58 -06:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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BitTracker.cpp
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[Hexagon] Fixes -Wrange-loop-analysis warnings
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2019-12-22 19:35:02 +01:00 |
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BitTracker.h
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CMakeLists.txt
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
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Hexagon.h
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Hexagon.td
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[TableGen] Support combining AssemblerPredicates with ORs
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2020-03-13 17:13:51 +00:00 |
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HexagonArch.h
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonAsmPrinter.cpp
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[MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex}
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2020-02-14 23:08:40 -08:00 |
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HexagonAsmPrinter.h
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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
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2020-02-13 22:08:55 -08:00 |
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HexagonBitSimplify.cpp
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonBitTracker.cpp
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[Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign()
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2020-04-01 14:08:28 +00:00 |
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HexagonBitTracker.h
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HexagonBlockRanges.cpp
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Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
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2019-08-01 23:27:28 +00:00 |
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HexagonBlockRanges.h
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HexagonBranchRelaxation.cpp
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[Alignment][NFC] Deprecate Align::None()
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2020-01-24 12:53:58 +01:00 |
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HexagonCallingConv.td
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HexagonCFGOptimizer.cpp
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HexagonCommonGEP.cpp
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Sink all InitializePasses.h includes
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2019-11-13 16:34:37 -08:00 |
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HexagonConstExtenders.cpp
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[Hexagon] Add a target feature to disable compound instructions
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2020-01-16 12:37:30 -06:00 |
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HexagonConstPropagation.cpp
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonCopyToCombine.cpp
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonDepArch.h
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonDepArch.td
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[TableGen] Support combining AssemblerPredicates with ORs
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2020-03-13 17:13:51 +00:00 |
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HexagonDepDecoders.inc
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[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm
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2020-01-23 09:38:54 -06:00 |
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HexagonDepIICHVX.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepIICScalar.td
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonDepInstrFormats.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepInstrInfo.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepITypes.h
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepITypes.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepMapAsm2Intrin.td
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[Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch
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2020-02-28 14:19:20 -06:00 |
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HexagonDepMappings.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepMask.h
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonDepOperands.td
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[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm
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2020-01-23 09:38:54 -06:00 |
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HexagonDepTimingClasses.h
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonEarlyIfConv.cpp
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Fix "pointer is null" static analyzer warnings. NFCI.
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2020-01-10 11:10:42 +00:00 |
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HexagonExpandCondsets.cpp
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Make more use of MachineInstr::mayLoadOrStore.
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2019-12-19 11:51:52 +00:00 |
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HexagonFixupHwLoops.cpp
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[Alignment][NFC] Deprecate Align::None()
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2020-01-24 12:53:58 +01:00 |
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HexagonFrameLowering.cpp
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[Alignment][NFC] Use more Align versions of various functions
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2020-04-02 09:00:53 +00:00 |
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HexagonFrameLowering.h
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ArrayRef'ize restoreCalleeSavedRegisters. NFCI.
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2020-02-29 09:50:23 +01:00 |
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HexagonGenExtract.cpp
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[IR] Split out target specific intrinsic enums into separate headers
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2019-12-11 18:02:14 -08:00 |
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HexagonGenInsert.cpp
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Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'
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2019-11-23 23:09:39 +01:00 |
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HexagonGenMux.cpp
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[Hexagon] Validate the iterators before converting them to mux.
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2019-11-14 13:01:16 -06:00 |
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HexagonGenPredicate.cpp
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Sink all InitializePasses.h includes
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2019-11-13 16:34:37 -08:00 |
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HexagonHardwareLoops.cpp
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CodeGen: Convert some TII hooks to use Register
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2020-04-03 14:52:54 -04:00 |
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HexagonHazardRecognizer.cpp
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HexagonHazardRecognizer.h
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HexagonIICHVX.td
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HexagonIICScalar.td
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HexagonInstrFormats.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonInstrFormatsV60.td
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HexagonInstrFormatsV65.td
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HexagonInstrInfo.cpp
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CodeGen: Convert some TII hooks to use Register
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2020-04-03 14:52:54 -04:00 |
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HexagonInstrInfo.h
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CodeGen: Convert some TII hooks to use Register
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2020-04-03 14:52:54 -04:00 |
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HexagonIntrinsics.td
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[Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch
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2020-02-28 14:19:20 -06:00 |
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HexagonIntrinsicsV5.td
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HexagonIntrinsicsV60.td
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[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
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2020-02-19 14:14:56 -06:00 |
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HexagonISelDAGToDAG.cpp
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[Alignment][NFC] Deprecate getMaxAlignment
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2020-03-18 14:48:45 +01:00 |
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HexagonISelDAGToDAG.h
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[AsmPrinter] De-capitalize Emit{Function,BasicBlock]* and Emit{Start,End}OfAsmFile
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2020-02-13 13:22:49 -08:00 |
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HexagonISelDAGToDAGHVX.cpp
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[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
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2020-02-19 14:14:56 -06:00 |
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HexagonISelLowering.cpp
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Clean up usages of asserting vector getters in Type
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2020-04-03 11:26:51 -07:00 |
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HexagonISelLowering.h
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Reland 7691790dfd1011d08f5468f63952d7690755aad4 with a MSAN fix
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2020-02-28 08:32:58 -06:00 |
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HexagonISelLoweringHVX.cpp
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[Hexagon] Only allow single HVX vector loads/stores in lowering
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2020-03-14 14:26:01 -05:00 |
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HexagonLoopIdiomRecognition.cpp
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Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC)."
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2020-01-04 18:44:38 +00:00 |
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HexagonMachineFunctionInfo.cpp
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HexagonMachineFunctionInfo.h
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Add support for Linux/Musl ABI
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2020-01-20 09:59:56 -06:00 |
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HexagonMachineScheduler.cpp
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HexagonMachineScheduler.h
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HexagonMapAsm2IntrinV62.gen.td
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HexagonMapAsm2IntrinV65.gen.td
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HexagonMCInstLower.cpp
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[Hexagon][NFC] Rename VK_Hexagon_PCREL to VK_PCREL
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2020-02-19 09:52:58 -06:00 |
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HexagonNewValueJump.cpp
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Sink all InitializePasses.h includes
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2019-11-13 16:34:37 -08:00 |
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HexagonOperands.td
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HexagonOptAddrMode.cpp
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
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HexagonOptimizeSZextends.cpp
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[IR] Split out target specific intrinsic enums into separate headers
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2019-12-11 18:02:14 -08:00 |
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HexagonPatterns.td
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[Hexagon] Fix fshl/fshr -> combine() bug identified in D75114
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2020-03-06 17:23:10 +00:00 |
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HexagonPatternsHVX.td
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[Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX
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2019-09-23 14:33:27 +00:00 |
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HexagonPatternsV65.td
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HexagonPeephole.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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HexagonPseudo.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonRDFOpt.cpp
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
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HexagonRegisterInfo.cpp
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[Hexagon] v67+ HVX register pairs should support either direction
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2020-02-14 12:43:43 -06:00 |
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HexagonRegisterInfo.h
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[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
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2020-01-19 14:20:37 -08:00 |
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HexagonRegisterInfo.td
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[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
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2020-02-19 14:14:56 -06:00 |
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HexagonSchedule.td
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonScheduleV5.td
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HexagonScheduleV55.td
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HexagonScheduleV60.td
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HexagonScheduleV62.td
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HexagonScheduleV65.td
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HexagonScheduleV66.td
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HexagonScheduleV67.td
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonScheduleV67T.td
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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HexagonSelectionDAGInfo.cpp
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HexagonSelectionDAGInfo.h
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HexagonSplitConst32AndConst64.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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HexagonSplitDouble.cpp
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CodeGen: Convert some TII hooks to use Register
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2020-04-03 14:52:54 -04:00 |
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HexagonStoreWidening.cpp
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[Alignment][NFC] Use Align version of getMachineMemOperand
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2020-03-30 15:46:27 +00:00 |
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HexagonSubtarget.cpp
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Make llvm::StringRef to std::string conversions explicit.
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2020-01-28 23:25:25 +01:00 |
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HexagonSubtarget.h
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[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
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2020-02-19 14:14:56 -06:00 |
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HexagonTargetMachine.cpp
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[Hexagon] Add support for Hexagon/HVX v67 ISA
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2020-01-20 16:16:49 -06:00 |
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HexagonTargetMachine.h
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HexagonTargetObjectFile.cpp
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[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile
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2020-03-20 21:57:34 -07:00 |
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HexagonTargetObjectFile.h
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HexagonTargetStreamer.h
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[MC] De-capitalize another set of MCStreamer::Emit* functions
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2020-02-14 19:26:52 -08:00 |
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HexagonTargetTransformInfo.cpp
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Clean up usages of asserting vector getters in Type
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2020-04-03 11:26:51 -07:00 |
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HexagonTargetTransformInfo.h
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[TTI][ARM][MVE] Refine gather/scatter cost model
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2020-03-11 10:23:41 +00:00 |
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HexagonVectorLoopCarriedReuse.cpp
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[IR] Split out target specific intrinsic enums into separate headers
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2019-12-11 18:02:14 -08:00 |
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HexagonVectorPrint.cpp
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[Hexagon] v67+ HVX register pairs should support either direction
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2020-02-14 12:43:43 -06:00 |
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HexagonVExtract.cpp
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[Hexagon] Handle stack realignment in hexagon-vextract
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2019-11-12 09:43:21 -06:00 |
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HexagonVLIWPacketizer.cpp
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[MC] Widen the functional unit type from 32 to 64 bits.
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2020-02-24 09:37:00 +01:00 |
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HexagonVLIWPacketizer.h
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[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
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2020-01-21 11:35:10 -06:00 |
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LLVMBuild.txt
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RDFCopy.cpp
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
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RDFCopy.h
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
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RDFDeadCode.cpp
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
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RDFDeadCode.h
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Move RDF from Hexagon to Codegen
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2020-03-17 12:43:14 -07:00 |
