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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/utils/TableGen
Craig Topper 48eff08046 [X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register.
This matches GNU assembler behavior. Operand size is determined
only from the destination register.

(cherry picked from commit 71b49aa438b22b02230fff30e8874ff756336e6d)
2020-07-20 15:44:42 +02:00
..
GlobalISel [TableGen] Avoid generating switch with just default 2020-06-02 19:48:07 +01:00
AsmMatcherEmitter.cpp [MC] Move deprecation infos from MCTargetDesc to MCInstrInfo 2020-03-29 21:20:40 +02:00
AsmWriterEmitter.cpp [TableGen] Fix non-standard escape warnings for braces in InstAlias 2020-05-28 09:36:24 +00:00
AsmWriterInst.cpp [MCInstPrinter] Pass Address parameter to MCOI::OPERAND_PCREL typed operands. NFC 2020-03-26 08:21:15 -07:00
AsmWriterInst.h [MCInstPrinter] Pass Address parameter to MCOI::OPERAND_PCREL typed operands. NFC 2020-03-26 08:21:15 -07:00
Attributes.cpp Sort EnumAttr so it matches Attribute::operator< 2020-04-26 17:00:25 +02:00
CallingConvEmitter.cpp [Alignment][NFC] Migrate HandleByVal to Align 2020-06-08 10:50:27 +00:00
CMakeLists.txt [openmp] Base of tablegen generated OpenMP common declaration 2020-06-23 10:32:32 -04:00
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp [Alignment][NFC] Transitionning more getMachineMemOperand call sites 2020-03-31 08:36:18 +00:00
CodeGenDAGPatterns.h
CodeGenHwModes.cpp
CodeGenHwModes.h
CodeGenInstruction.cpp [TableGen] Handle (outs variable_ops) 2020-06-04 16:07:33 +03:00
CodeGenInstruction.h
CodeGenIntrinsics.h [IR] NoFree IntrinsicProperty. 2020-06-30 11:26:00 +02:00
CodeGenMapTable.cpp
CodeGenRegisters.cpp [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness. 2020-03-18 19:52:23 +00:00
CodeGenRegisters.h [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness. 2020-03-18 19:52:23 +00:00
CodeGenSchedule.cpp Suppress a few -Wunreachable-code warnings. 2020-03-25 13:55:42 -04:00
CodeGenSchedule.h
CodeGenTarget.cpp [MVT] Add new MVT types for RISC-V vector. 2020-07-01 01:07:50 +08:00
CodeGenTarget.h
CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp llvm-tblgen -gen-dag-isel: Hoist SmallVector TmpBuf 2020-04-25 20:41:04 -07:00
DAGISelMatcherGen.cpp [TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator 2020-05-13 10:17:03 +01:00
DAGISelMatcherOpt.cpp
DFAEmitter.cpp
DFAEmitter.h DFAEmitter.h - remove unnecessary headers. NFC. 2020-05-08 14:53:10 +01:00
DFAPacketizerEmitter.cpp
DirectiveEmitter.cpp [flang][openacc] OpenACC 3.0 parser 2020-07-14 14:29:40 -04:00
DisassemblerEmitter.cpp
ExegesisEmitter.cpp
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
GICombinerEmitter.cpp [gicombiner] Allow disable-rule option to disable all-except-... 2020-06-16 16:57:16 -07:00
GlobalISelEmitter.cpp TableGen/GlobalISel: Partially fix nontrivial, custom predicates 2020-07-14 14:26:51 -04:00
InfoByHwMode.cpp
InfoByHwMode.h
InstrDocsEmitter.cpp
InstrInfoEmitter.cpp TableGen: Don't reconstruct CodeGenDAGTarget 2020-05-23 12:15:44 -04:00
IntrinsicEmitter.cpp [IR] NoFree IntrinsicProperty. 2020-06-30 11:26:00 +02:00
LLVMBuild.txt
OptEmitter.cpp
OptEmitter.h
OptParserEmitter.cpp Start adding support for generating CC1 command lines from CompilerInvocation 2020-06-24 18:05:05 +01:00
OptRSTEmitter.cpp
PredicateExpander.cpp
PredicateExpander.h
PseudoLoweringEmitter.cpp
RegisterBankEmitter.cpp Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes" 2020-03-20 11:02:50 +01:00
RegisterInfoEmitter.cpp
RISCVCompressInstEmitter.cpp [RISCV] Support negative constants in CompressInstEmitter 2020-03-26 15:23:38 +00:00
SDNodeProperties.cpp
SDNodeProperties.h
SearchableTableEmitter.cpp [TableGen] Add error messages 2020-06-23 11:52:12 +02:00
SequenceToOffsetTable.h
SubtargetEmitter.cpp
SubtargetFeatureInfo.cpp [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
SubtargetFeatureInfo.h
TableGen.cpp [flang][openmp] Check clauses allowed semantic with tablegen generated map 2020-07-11 12:45:12 -04:00
TableGenBackends.h [flang][openmp] Check clauses allowed semantic with tablegen generated map 2020-07-11 12:45:12 -04:00
tdtags
Types.cpp
Types.h
WebAssemblyDisassemblerEmitter.cpp
WebAssemblyDisassemblerEmitter.h
X86DisassemblerShared.h
X86DisassemblerTables.cpp [X86] Remove MODRM_SPLITREGM from the disassembler tables. 2020-07-03 00:16:20 -07:00
X86DisassemblerTables.h
X86EVEX2VEXTablesEmitter.cpp
X86FoldTablesEmitter.cpp
X86ModRMFilters.cpp [X86-64] Support Intel AMX instructions 2020-07-02 08:57:04 +08:00
X86ModRMFilters.h [X86-64] Support Intel AMX instructions 2020-07-02 08:57:04 +08:00
X86RecognizableInstr.cpp [X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register. 2020-07-20 15:44:42 +02:00
X86RecognizableInstr.h [X86-64] Support Intel AMX instructions 2020-07-02 08:57:04 +08:00