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4b6f06420e
The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
51 lines
1.3 KiB
LLVM
51 lines
1.3 KiB
LLVM
; Test the Test Data Class instruction, as used by fpclassify.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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;
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declare float @llvm.fabs.f32(float)
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declare double @llvm.fabs.f64(double)
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declare fp128 @llvm.fabs.f128(fp128)
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define i32 @fpc(double %x) {
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entry:
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; CHECK-LABEL: fpc
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; CHECK-DAG: lhi %r2, 5
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; CHECK-DAG: ltdbr %f0, %f0
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; CHECK: je [[RET:.L.*]]
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%testeq = fcmp oeq double %x, 0.000000e+00
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br i1 %testeq, label %ret, label %nonzero, !prof !1
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nonzero:
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; CHECK-DAG: lhi %r2, 1
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; CHECK-DAG: cdbr %f0, %f0
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; CHECK: jo [[RET]]
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%testnan = fcmp uno double %x, 0.000000e+00
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br i1 %testnan, label %ret, label %nonzeroord, !prof !1
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nonzeroord:
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; CHECK-DAG: lhi %r2, 2
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; CHECK-DAG: tcdb %f0, 48
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; CHECK: jl [[RET]]
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%abs = tail call double @llvm.fabs.f64(double %x)
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%testinf = fcmp oeq double %abs, 0x7FF0000000000000
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br i1 %testinf, label %ret, label %finite, !prof !1
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finite:
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; CHECK-DAG: lhi %r2, 3
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; CHECK-DAG: tcdb %f0, 831
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; CHECK: blr %r14
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; CHECK: lhi %r2, 4
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%testnormal = fcmp uge double %abs, 0x10000000000000
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%finres = select i1 %testnormal, i32 3, i32 4
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br label %ret
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ret:
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; CHECK: [[RET]]:
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; CHECK: br %r14
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%res = phi i32 [ 5, %entry ], [ 1, %nonzero ], [ 2, %nonzeroord ], [ %finres, %finite ]
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ret i32 %res
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}
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!1 = !{!"branch_weights", i32 1, i32 1}
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