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https://github.com/RPCS3/llvm-mirror.git
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7162966fa9
There were various hacks used to try to avoid making s1 SGPR vs. s1 VCC ambiguous after constraining the register before we had a strategy to deal with this. This also attempted to handle undef operands, which are now illegal gMIR.
177 lines
4.0 KiB
YAML
177 lines
4.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2> %t | FileCheck -check-prefixes=GCN %s
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# RUN: FileCheck -check-prefix=ERR %s < %t
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# ERR-NOT: remark:
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# ERR: remark: <unknown>:0:0: cannot select: G_BRCOND %1:sgpr(s1), %bb.1 (in function: brcond_sgpr)
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# ERR-NEXT: remark: <unknown>:0:0: cannot select: G_BRCOND %1:vgpr(s1), %bb.1 (in function: brcond_vgpr)
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# ERR-NOT: remark:
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---
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name: brcond_scc
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_scc
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY2]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: bb.1:
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bb.0:
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liveins: $sgpr0, $sgpr1
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
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G_BRCOND %2, %bb.1
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bb.1:
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...
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---
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name: brcond_scc_impdef
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_scc_impdef
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN: $scc = COPY [[DEF]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: bb.1:
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bb.0:
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liveins: $sgpr0, $sgpr1
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%0:sgpr(s32) = G_IMPLICIT_DEF
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G_BRCOND %0, %bb.1
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bb.1:
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...
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---
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name: brcond_scc_br
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_scc_br
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
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; GCN: $scc = COPY [[COPY2]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.1
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: bb.2:
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bb.0:
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liveins: $sgpr0, $sgpr1
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
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G_BRCOND %2, %bb.1
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G_BR %bb.1
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bb.1:
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bb.2:
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...
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---
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name: brcond_vcc
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_vcc
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: $vcc = COPY [[V_CMP_EQ_U32_e64_]]
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.1:
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
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G_BRCOND %2, %bb.1
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bb.1:
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...
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# Don't try to select this.
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---
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name: brcond_sgpr
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_sgpr
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
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; GCN: G_BRCOND [[TRUNC]](s1), %bb.1
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; GCN: bb.1:
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bb.0:
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liveins: $sgpr0, $sgpr1
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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G_BRCOND %1, %bb.1
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bb.1:
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...
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# Don't try to select this.
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---
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name: brcond_vgpr
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legalized: true
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regBankSelected: true
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body: |
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; GCN-LABEL: name: brcond_vgpr
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; GCN: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
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; GCN: G_BRCOND [[TRUNC]](s1), %bb.1
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; GCN: bb.1:
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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G_BRCOND %1, %bb.1
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bb.1:
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...
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