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https://github.com/RPCS3/llvm-mirror.git
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1536faf532
Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D103057
93 lines
2.0 KiB
LLVM
93 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 | FileCheck %s
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;
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; Check that CodeGenPrepare transforms these functions to use
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; uadd.with.overflow / usub.with.overflow intrinsics so that the compare
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; instruction is eliminated.
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define i32 @uaddo_32(i32 %arg) {
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; CHECK-LABEL: uaddo_32:
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; CHECK: alhsik %r0, %r2, -1
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; CHECK: locrnle %r2, %r0
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; CHECK: br %r14
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bb:
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%tmp10 = icmp ne i32 %arg, 0
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%tmp11 = add nsw i32 %arg, -1
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%tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
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ret i32 %tmp12
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}
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define i64 @uaddo_64(i64 %arg) {
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; CHECK-LABEL: uaddo_64:
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; CHECK: alghsik %r0, %r2, -1
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; CHECK: locgrnle %r2, %r0
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; CHECK: br %r14
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bb:
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%tmp10 = icmp ne i64 %arg, 0
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%tmp11 = add nsw i64 %arg, -1
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%tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
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ret i64 %tmp12
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}
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define i32 @usubo_32(i32 %arg) {
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; CHECK-LABEL: usubo_32:
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; CHECK: alhsik %r0, %r2, -1
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; CHECK: locrle %r2, %r0
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; CHECK: br %r14
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bb:
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%tmp10 = icmp eq i32 %arg, 0
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%tmp11 = sub nsw i32 %arg, 1
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%tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
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ret i32 %tmp12
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}
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define i64 @usubo_64(i64 %arg) {
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; CHECK-LABEL: usubo_64:
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; CHECK: alghsik %r0, %r2, -1
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; CHECK: locgrle %r2, %r0
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; CHECK: br %r14
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bb:
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%tmp10 = icmp eq i64 %arg, 0
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%tmp11 = sub nsw i64 %arg, 1
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%tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
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ret i64 %tmp12
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}
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define i32 @optbranch_32(i32 %Arg) {
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; CHECK-LABEL: optbranch_32:
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; CHECK: alhsik %r2, %r2, 1
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; CHECK-NEXT: bler %r14
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; CHECK-NEXT: .LBB4_1:
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; CHECK-NEXT: lhi %r2, -1
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; CHECK-NEXT: br %r14
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bb:
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%i1 = icmp eq i32 %Arg, -1
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br i1 %i1, label %bb2, label %bb3
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bb2:
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ret i32 -1
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bb3:
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%i4 = add nuw i32 %Arg, 1
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ret i32 %i4
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}
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define i64 @optbranch_64(i64 %Arg) {
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; CHECK-LABEL: optbranch_64:
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; CHECK: alghsik %r2, %r2, 1
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; CHECK-NEXT: bler %r14
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; CHECK-NEXT: .LBB5_1:
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; CHECK-NEXT: lghi %r2, -1
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; CHECK-NEXT: br %r14
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bb:
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%i1 = icmp eq i64 %Arg, -1
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br i1 %i1, label %bb2, label %bb3
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bb2:
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ret i64 -1
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bb3:
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%i4 = add nuw i64 %Arg, 1
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ret i64 %i4
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}
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