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llvm-mirror/test/CodeGen/AMDGPU
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Jay Foad 453349344b [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset 
Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

D106284 did this for SelectionDAG. This is the corresponding fix for
GlobalISel.

Differential Revision: https://reviews.llvm.org/D106451
2021-07-26 14:27:30 +01:00
..
GlobalISel [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
32-bit-local-address-space.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
aa-points-to-constant-memory.ll
acc-ldst.ll
accvgpr-copy.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
add3.ll
add_i1.ll
add_i64.ll
add_i128.ll
add_shl.ll
add-debug.ll
add.i16.ll
add.ll
add.v2i16.ll
addrspacecast-captured.ll
addrspacecast-constantexpr.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
addrspacecast-initializer-unsupported.ll [AMDGPU] Rename "LDS lowering" pass name. 2021-04-14 20:19:53 +05:30
addrspacecast-initializer.ll
addrspacecast.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
adjust-writemask-invalid-copy.ll
adjust-writemask-vectorized.ll
agpr-csr.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
agpr-register-count.ll [AMDGPU] Improve register computation for indirect calls 2021-07-20 13:48:50 +02:00
agpr-remat.ll
alignbit-pat.ll
alloc-aligned-tuples-gfx90a.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
alloc-aligned-tuples-gfx908.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
alloc-all-regs-reserved-in-class.mir
alloca.ll
always-uniform.ll
amd.endpgm.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
amdgcn-ieee.ll
amdgcn-load-offset-from-reg.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
amdgcn.bitcast.ll
amdgcn.private-memory.ll
amdgpu-alias-analysis.ll
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-fold-binop-select.ll Reapply [ConstantFold] Fold more operations to poison 2021-05-13 16:04:12 +02:00
amdgpu-codegenprepare-foldnegate.ll [AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask 2021-06-18 13:04:12 -06:00
amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Update generated checks. NFC. 2021-06-18 10:49:02 +01:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
amdgpu-codegenprepare-mul24.ll
amdgpu-function-calls-option.ll
amdgpu-inline.ll
amdgpu-late-codegenprepare.ll AMDGPU: Fix assert on constant load from addrspacecasted pointer 2021-05-11 20:12:20 -04:00
amdgpu-mul24-knownbits.ll
amdgpu-reloc-const.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
amdgpu-shader-calling-convention.ll
amdgpu-unroll-threshold.ll
amdgpu.private-memory.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll
amdpal_scratch_mergedshader.ll
amdpal-callable.ll [AMDGPU] Improve register computation for indirect calls 2021-07-20 13:48:50 +02:00
amdpal-cs.ll
amdpal-elf.ll [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines 2021-06-29 11:50:31 -07:00
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-msgpack-cs.ll
amdpal-msgpack-default.ll
amdpal-msgpack-denormal.ll
amdpal-msgpack-dx10-clamp.ll
amdpal-msgpack-es.ll
amdpal-msgpack-gs.ll
amdpal-msgpack-hs.ll
amdpal-msgpack-ieee.ll
amdpal-msgpack-ls.ll
amdpal-msgpack-ps.ll
amdpal-msgpack-psenable.ll
amdpal-msgpack-vs.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
and_or.ll
and-gcn.ll
and.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
andorbitset.ll
andorn2.ll
andorxorinvimm.ll
annotate-kernel-features-hsa-call.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
annotate-kernel-features-hsa.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
annotate-kernel-features.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
annotate-noclobber.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll [AMDGPU] Regenerate anyext test checks 2021-07-25 14:05:08 +01:00
are-loads-from-same-base-ptr.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll
asm-printer-check-vcc.mir
at-least-one-def-value-assert.mir
atomic_cmp_swap_local.ll
atomic_load_add.ll
atomic_load_local.ll
atomic_load_sub.ll
atomic_optimizations_buffer.ll
atomic_optimizations_global_pointer.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
atomic_optimizations_local_pointer.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
atomic_optimizations_pixelshader.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
atomic_optimizations_raw_buffer.ll
atomic_optimizations_struct_buffer.ll
atomic_store_local.ll
atomicrmw-nand.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
attr-amdgpu-flat-work-group-size-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
attr-amdgpu-flat-work-group-size.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
attr-amdgpu-num-sgpr.ll
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll
bfi_int.ll
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll
bitcast-v4f16-v4i16.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
branch-relaxation-debug-info.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-relaxation-gfx10-branch-offset-bug.ll
branch-relaxation-inst-size-gfx10.ll
branch-relaxation.ll
branch-uniformity.ll
break-smem-soft-clauses.mir AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
break-vmem-soft-clauses.mir
bswap.ll
buffer-intrinsics-mmo-offsets.ll [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
buffer-schedule.ll [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
bug-sdag-scheduler-cycle.ll
bug-vopc-commute.ll
build_vector.ll
build-vector-insert-elt-infloop.ll
build-vector-packed-partial-undef.ll
bundle-latency.mir
bypass-div.ll [AMDGPU] Improve killed check for vgpr optimization 2021-07-21 15:24:59 +02:00
byval-frame-setup.ll
call_fs.ll
call-argument-types.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
call-constant.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
call-constexpr.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
call-encoding.ll
call-graph-register-usage.ll [AMDGPU] Improve register computation for indirect calls 2021-07-20 13:48:50 +02:00
call-preserved-registers.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
call-return-types.ll
call-skip.ll
call-to-kernel-undefined.ll
call-to-kernel.ll
call-waitcnt.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
call-waw-waitcnt.mir
callee-frame-setup.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
callee-special-input-sgprs-fixed-abi.ll
callee-special-input-sgprs.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
callee-special-input-vgprs-packed.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
callee-special-input-vgprs.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
calling-conventions.ll
captured-frame-index.ll
carryout-selection.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
cayman-loop-bug.ll
cc-sgpr-limit.ll
cc-sgpr-over-limit.ll
cc-update.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
cf_end.ll
cf-loop-on-constant.ll [LSR] Fix for pre-indexed generated constant offset 2021-04-15 16:44:42 +01:00
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes-gfx908.ll
cgp-addressing-modes-gfx1030.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
cgp-addressing-modes.ll
cgp-bitfield-extract.ll
chain-hi-to-lo.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
change-scc-to-vcc.mir [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
clamp-modifier.ll
clamp-omod-special-case.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
clamp.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
cluster_stores.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
cluster-flat-loads-postra.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cluster-flat-loads.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cmp_shrink.mir
cndmask-no-def-vcc.ll
coalesce-identity-copies-undef-subregs.mir
coalesce-vgpr-alignment.ll
coalescer_distribute.ll
coalescer_remat.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
coalescer-extend-pruned-subrange.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-identical-values-undef.mir
coalescer-remat-dead-use.mir Prevent dead uses in register coalescer after rematerialization 2021-07-21 15:19:55 -07:00
coalescer-removepartial-extend-undef-subrange.mir
coalescer-subranges-another-copymi-not-live.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-subranges-another-prune-error.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-subranges-prune-kill-copy.mir
coalescer-subreg-join.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-subregjoin-fullcopy.mir
coalescer-with-subregs-bad-identical.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescing_makes_lanes_undef.mir
coalescing-subreg-was-undef-but-became-def.mir
coalescing-with-subregs-in-loop-bug.mir
code-object-v3.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
codegen-prepare-addrmode-sext.ll
collapse-endcf2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
collapse-endcf-broken.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
collapse-endcf.ll [AMDGPU] Add Optimize VGPR LiveRange Pass. 2021-06-21 15:25:55 +08:00
collapse-endcf.mir
combine_vloads.ll
combine-add-zext-xor.ll
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
combine-sreg64-inits.mir [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
comdat.ll
commute_modifiers.ll
commute-compares.ll
commute-shifts.ll
commute-vop3.mir [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll
computeNumSignBits-mul.ll
concat_vectors.ll
constant-address-space-32bit.ll
constant-fold-imm-immreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
control-flow-optnone.ll
convergent-inlineasm.ll
copy_phys_vgpr64.mir [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
copy-illegal-type.ll
copy-overlap-vgpr-kill.mir
copy-to-reg.ll
couldnt-join-subrange-3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cross-block-use-is-not-abi-copy.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
cse-phi-incoming-val.ll
csr-gfx10.ll
csr-sgpr-spill-live-ins.mir
ctlz_zero_undef.ll
ctlz.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
ctpop16.ll [AMDGPU] Regenerate ctpop16 test checks 2021-07-25 14:05:09 +01:00
ctpop64.ll
ctpop.ll
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence-atomic.ll [AMDGPU] Update gfx90a memory model support 2021-04-07 22:17:58 +00:00
dag-divergence.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll
dagcombine-setcc-select.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dbg-value-ends-sched-region.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
dce-disjoint-intervals.mir
dead_copy.mir
dead-lane.mir
dead-machine-elim-after-dead-lane.ll
debug_frame.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
debug-value2.ll
debug-value-scheduler-crash.mir
debug-value.ll VirtRegMap: Preserve LiveDebugVariables 2021-05-27 10:40:14 -04:00
debug.ll
default-fp-mode.ll
detect-dead-lanes.mir
direct-indirect-call.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
directive-amdgcn-target.ll [AMDGPU] Add gfx1035 target 2021-06-24 14:32:41 -04:00
disable_form_clauses.ll
disconnected-predset-break-bug.ll
div_i128.ll
diverge-extra-formal-args.ll
diverge-interp-mov-lower.ll
diverge-switch-default.ll
divergence-at-use.ll
divergent-branch-uniform-condition.ll
divrem24-assume.ll
dpp64_combine.ll
dpp64_combine.mir
dpp_combine.ll
dpp_combine.mir [AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used 2021-04-20 09:17:52 +01:00
drop-mem-operand-move-smrd.ll
ds_gws_align.ll [AMDGPU] All GWS instructions need aligned VGPR on gfx90a 2021-06-01 17:08:03 -07:00
ds_read2_offset_order.ll [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering. 2021-06-07 18:00:41 +05:30
ds_read2_superreg.ll
ds_read2.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
ds_read2st64.ll
ds_write2.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
ds_write2st64.ll
ds-alignment.ll GlobalISel: Avoid use of G_INSERT in insertParts 2021-06-08 14:44:24 -04:00
ds-combine-large-stride.ll
ds-combine-with-dependence.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
duplicate-attribute-indirect.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll Revert "Revert "Temporarily do not drop volatile stores before unreachable"" 2021-07-09 11:44:34 -04:00
early-tailduplicator-nophis.mir
early-term.mir [AMDGPU] Allow frontends to disable null export for pixel shaders 2021-07-22 10:20:46 +09:00
elf-header-flags-mach.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
elf-header-flags-sramecc.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
elf-header-flags-xnack.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
elf-header-osabi.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
elf-notes.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
elf.ll
elf.metadata.ll
elf.r600.ll
else.ll
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
enqueue-kernel.ll
exceed-max-sgprs.ll Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular) 2021-06-22 09:55:20 -07:00
expand-atomicrmw-syncscope.ll [AMDGPU] Update gfx90a memory model support 2021-04-07 22:17:58 +00:00
expand-scalar-carry-out-select-user.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
expand-si-indirect.mir
extend-bit-ops-i16.ll
extload-align.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
extload-private.ll
extload.ll
extra-sroa-after-unroll.ll
extract_subvector_vec4_vec3.ll [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
extract_vector_dynelt.ll
extract_vector_elt-f16.ll
extract_vector_elt-f64.ll
extract_vector_elt-i8.ll
extract_vector_elt-i16.ll
extract_vector_elt-i64.ll
extract-load-i1.ll
extract-lowbits.ll
extract-subvector-equal-length.ll
extract-subvector.ll
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll
fabs.f64.ll
fabs.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
fadd64.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
fadd-fma-fmul-combine.ll
fadd.f16.ll
fadd.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fail-select-buffer-atomic-fadd.ll
fast-ra-kills-vcc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fast-regalloc-bundles.mir
fast-unaligned-load-store.global.ll [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
fast-unaligned-load-store.private.ll [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
fastregalloc-illegal-subreg-physreg.mir
fastregalloc-self-loop-heuristic.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fcanonicalize-elimination.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fcanonicalize.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fcanonicalize.ll
fceil64.ll
fceil.ll
fcmp64.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fconst64.ll
fcopysign.f16.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv32-to-rcp-folding.ll
fdiv-nofpexcept.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
fdiv.f16.ll
fdiv.f64.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fdiv.ll
fdot2.ll
fence-barrier.ll
fence-lds-read2-write2.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
ffloor.f64.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
ffloor.ll
fix-frame-ptr-reg-copy-livein.ll
fix-sgpr-copies.mir
fix-vgpr-copies.mir
fix-wwm-vgpr-copy.ll
flat_atomics_i64.ll
flat_atomics.ll
flat-address-space.ll
flat-error-unsupported-gpu-hsa.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
flat-for-global-subtarget-feature.ll
flat-load-clustering.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
flat-offset-bug.ll
flat-scratch-fold-fi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
flat-scratch-init.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
flat-scratch-reg.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
flat-scratch.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
floor.ll
fma-combine.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fma.f64.ll
fma.ll
fmac.sdwa.ll
fmad-formation-fmul-distribute-denormal-mode.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
fmad.ll
fmax3.f64.ll
fmax3.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fmax_legacy.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fmax_legacy.f64.ll
fmax_legacy.ll
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
fmaxnum.r600.ll
fmed3.ll
fmin3.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fmin_legacy.f64.ll
fmin_legacy.ll
fmin.ll
fminnum.f64.ll
fminnum.ll
fminnum.r600.ll
fmul64.ll
fmul-2-combine-multi-use.ll
fmul.f16.ll
fmul.ll
fmuladd.f16.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fmuladd.f32.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fmuladd.f64.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fmuladd.v2f16.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fnearbyint.ll
fneg-combines.ll AMDGPU: Fix infinite loop in DAG combine with fneg + fma 2021-06-18 19:09:03 -04:00
fneg-combines.si.ll
fneg-fabs.f16.ll
fneg-fabs.f64.ll
fneg-fabs.ll
fneg-fold-legalize-dag-increase-insts.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
fneg.f16.ll
fneg.f64.ll
fneg.ll
fold_16bit_imm.mir
fold_acc_copy_into_valu.mir
fold-cndmask-wave32.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-cndmask.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-fi-mubuf.mir
fold-fi-operand-shrink.mir
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
fold-imm-f16-f32.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fold-immediate-operand-shrink-with-carry.mir
fold-immediate-operand-shrink.mir
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-operands-remove-m0-redef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fold-over-exec.mir
fold-readlane.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-reload-into-exec.mir
fold-reload-into-m0.mir
fold-sgpr-copy.mir
fold-sgpr-multi-imm.mir
fold-vgpr-copy.mir
force-alwaysinline-lds-global-address-codegen.ll [AMDGPU] Disable forceful inline of non-kernel functions which use LDS. 2021-04-15 09:12:56 +05:30
force-alwaysinline-lds-global-address.ll [AMDGPU] Disable forceful inline of non-kernel functions which use LDS. 2021-04-15 09:12:56 +05:30
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp64-atomics-gfx90a.ll [AMDGPU] Update gfx90a memory model support 2021-06-30 04:05:22 +00:00
fp_to_sint.f64.ll
fp_to_sint.ll [amdgpu] Improve the from f32 to i64. 2021-06-19 12:46:48 -04:00
fp_to_uint.f64.ll
fp_to_uint.ll [amdgpu] Improve the from f32 to i64. 2021-06-19 12:46:48 -04:00
fp-atomic-to-s_denormmode.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fp-classify.ll
fpext-free.ll [DAGCombine] Check reassoc flags in aggressive fsub fusion 2021-06-23 13:59:40 +00:00
fpext.f16.ll
fpext.ll
fpow.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fptosi.f16.ll [AMDGPU] Select V_CVT_*16_F16 more often 2021-05-05 08:57:51 +01:00
fptoui.f16.ll [AMDGPU] Select V_CVT_*16_F16 more often 2021-05-05 08:57:51 +01:00
fptrunc.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
frame-lowering-entry-all-sgpr-used.mir
frame-lowering-fp-adjusted.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
frame-setup-without-sgpr-to-vgpr-spills.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
frem.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fshl.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
fshr.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
fsqrt.f64.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fsqrt.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fsub64.ll
fsub.f16.ll
fsub.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll
function-call-relocs.ll
function-returns.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
gds-atomic.ll
gep-address-space.ll
gfx10-vop-literal.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
gfx90a-enc.ll
gfx902-without-xnack.ll
gfx-callable-argument-types.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
gfx-callable-preserved-registers.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
gfx-callable-return-types.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
global_atomics_i64.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global_atomics.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global_smrd_cfg.ll
global_smrd.ll
global-atomics-fp-wrong-subtarget.ll AMDGPU: Restore atomic fp feature on FP atomic instruction definitions 2021-04-22 21:32:01 -04:00
global-atomics-fp.ll [AMDGPU] Move atomic expand past infer address spaces 2021-07-06 15:53:32 -07:00
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-load-saddr-to-vaddr.ll [AMDGPU] Regenerate global-load-saddr-to-vaddr test checks 2021-07-25 14:05:10 +01:00
global-saddr-atomics.gfx908.ll
global-saddr-atomics.gfx1030.ll
global-saddr-atomics.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
global-saddr-load.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global-saddr-store.ll
global-smrd-unknown.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
global-variable-relocs.ll
greedy-broken-ssa-verifier-error.mir
gv-const-addrspace.ll
gv-offset-folding.ll
gws-hazards.mir [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
half.ll [AMDGPU] Regenerate half test checks 2021-07-25 14:05:08 +01:00
hard-clauses.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
hazard-buffer-store-v-interp.mir
hazard-hidden-bundle.mir
hazard-in-bundle.mir
hazard-inlineasm.mir
hazard-kill.mir
hazard-pass-ordering.mir
hazard-recognizer-meta-insts.mir
hazard.mir
high-bits-zeroed-16-bit-ops.mir AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
hip.extern.shared.array.ll
hoist-cond.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
hsa-func.ll
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueue-kernel-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-enqueue-kernel.ll
hsa-metadata-from-llvm-ir-full-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-from-llvm-ir-full.ll
hsa-metadata-hidden-args-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-hidden-args.ll
hsa-metadata-hostcall-absent-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-hostcall-absent.ll
hsa-metadata-hostcall-present-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-hostcall-present.ll
hsa-metadata-images-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-images.ll
hsa-metadata-invalid-ocl-version-1-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props-v3.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
hsa-metadata-kernel-code-props.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
hsa-metadata-wavefrontsize.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-note-no-func.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa.ll [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines 2021-06-29 11:50:31 -07:00
huge-number-operand-folds.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
huge-private-buffer.ll
i1_copy_phi_with_phi_incoming_value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
i1-copies-rpo.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
i1-copy-from-loop.ll
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
i1-copy-phi.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll [DAG] Enable foldSelectOfBinops on select(setcc(),binop(),binop()) calls 2021-07-18 18:38:59 +01:00
idot2.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot4s.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot4u.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot8s.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
idot8u.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
illegal-sgpr-to-vgpr-copy.ll
image_ls_mipmap_zero.ll
image-attributes.ll
image-load-d16-tfe.ll
image-resource-id.ll
image-sample-waterfall.ll [AMDGPU] Optimize VGPR LiveRange in waterfall loops 2021-07-13 12:15:08 +02:00
image-schedule.ll
img-nouse-adjust.ll
imm16.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
imm.ll
immv216.ll
implicit-def-muse.ll
indirect-addressing-si-gfx9.ll AMDGPU: Fix assert on m0_lo16/m0_hi16 2021-06-18 18:48:53 -04:00
indirect-addressing-si-noopt.ll
indirect-addressing-si-pregfx9.ll
indirect-addressing-si.ll
indirect-addressing-term.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
indirect-call.ll [AMDGPU] Improve register computation for indirect calls 2021-07-20 13:48:50 +02:00
indirect-private-64.ll
infer-addrpace-pipeline.ll
infer-uniform-load-shader.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.i128.ll [AMDGPU] Tidy SReg/SGPR definitions using template class 2021-07-17 11:26:46 +09:00
inline-asm.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
inline-attr.ll Reapply [IR] Don't mark mustprogress as type attribute 2021-07-09 20:57:44 +02:00
inline-calls.ll
inline-constraints.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
inline-maxbb.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_dynelt.ll
insert_vector_elt.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
insert_vector_elt.v2i16.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
insert_vector_elt.v2i16.subtest-saddr.ll
insert-branch-w32.mir
insert-skip-from-vcc.mir
insert-skips-flat-vmem-ds.mir
insert-skips-gws.mir
insert-skips-ignored-insts.mir
insert-subvector-unused-scratch.ll
insert-waitcnts-callee.mir
insert-waitcnts-exp.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
inserted-wait-states.mir
internalize.ll
invalid-addrspacecast.ll
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ipra-regmask.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
ipra.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
jump-address.ll
kcache-fold.ll
kernarg-size.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
kernarg-stack-alignment.ll
kernel-args.ll
kernel-argument-dag-lowering.ll
kill-infinite-loop.ll [AMDGPU] Don't handle export done when unify exit nodes 2021-07-14 14:54:37 +08:00
known-never-nan.ll
known-never-snan.ll
knownbits-recursion.ll
large-alloca-compute.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
large-alloca-graphics.ll
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lcssa-optnone.ll
lds_atomic_f32.ll
lds-alignment.ll [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering. 2021-06-07 18:00:41 +05:30
lds-bounds.ll
lds-branch-vmem-hazard.mir
lds-global-non-entry-func.ll [AMDGPU] Rename "LDS lowering" pass name. 2021-04-14 20:19:53 +05:30
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-misaligned-bug.ll [AMDGPU] Only use ds_read/write_b128 for alignment >= 16 2021-04-08 08:12:05 +05:30
lds-oqap-crash.ll
lds-output-queue.ll
lds-relocs.ll [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines 2021-06-29 11:50:31 -07:00
lds-size.ll
lds-zero-initializer.ll
legalize-fp-load-invariant.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
limit-soft-clause-reg-pressure.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lit.local.cfg
literals.ll
liveness.mir
llc-pipeline.ll [AMDGPU] Move perfhint analysis 2021-07-21 13:06:49 -07:00
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.csub.ll
llvm.amdgcn.atomic.dec.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
llvm.amdgcn.atomic.fadd.gfx90a.ll
llvm.amdgcn.atomic.fadd.ll
llvm.amdgcn.atomic.inc.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
llvm.amdgcn.ballot.i32.ll
llvm.amdgcn.ballot.i64.ll
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.dwordx3.ll
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.dwordx3.ll
llvm.amdgcn.buffer.store.format.d16.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.append.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.barrier.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.init.ll
llvm.amdgcn.ds.gws.sema.br.ll
llvm.amdgcn.ds.gws.sema.p.ll
llvm.amdgcn.ds.gws.sema.release.all.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.sema.v.ll
llvm.amdgcn.ds.ordered.add.gfx10.ll
llvm.amdgcn.ds.ordered.add.ll
llvm.amdgcn.ds.ordered.swap.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.exp.prim.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fma.legacy.ll
llvm.amdgcn.fmad.ftz.f16.ll
llvm.amdgcn.fmad.ftz.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.a16.dim.ll
llvm.amdgcn.image.a16.encode.ll
llvm.amdgcn.image.atomic.dim.ll
llvm.amdgcn.image.d16.dim.ll
llvm.amdgcn.image.dim.gfx90a.ll
llvm.amdgcn.image.dim.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
llvm.amdgcn.image.gather4.d16.dim.ll
llvm.amdgcn.image.gather4.dim.ll [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions 2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.gather4.o.dim.ll [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions 2021-07-22 10:42:15 +09:00
llvm.amdgcn.image.getlod.dim.ll
llvm.amdgcn.image.load.a16.d16.ll
llvm.amdgcn.image.load.a16.ll
llvm.amdgcn.image.msaa.load.x.ll
llvm.amdgcn.image.nsa.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.dim.gfx90a.ll
llvm.amdgcn.image.sample.dim.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.g16.a16.dim.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.g16.encode.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.g16.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.ltolz.ll
llvm.amdgcn.image.sample.o.dim.ll [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions 2021-07-22 10:42:15 +09:00
llvm.amdgcn.image.store.a16.d16.ll
llvm.amdgcn.image.store.a16.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
llvm.amdgcn.init.exec.ll
llvm.amdgcn.init.exec.wave32.ll
llvm.amdgcn.interp.f16.ll
llvm.amdgcn.interp.ll
llvm.amdgcn.intersect_ray.ll Reland "[AMDGPU] Add gfx1013 target" 2021-06-08 21:15:35 -04:00
llvm.amdgcn.is.private.ll
llvm.amdgcn.is.shared.ll
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.bf16.ll
llvm.amdgcn.mfma.gfx90a.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
llvm.amdgcn.mfma.i8.ll
llvm.amdgcn.mfma.ll
llvm.amdgcn.mov.dpp8.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
llvm.amdgcn.mul.u24.ll
llvm.amdgcn.perm.ll [AMDGPU] Expose __builtin_amdgcn_perm for v_perm_b32 2021-05-06 16:17:33 -07:00
llvm.amdgcn.permlane.ll
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.raw.buffer.atomic.fadd.ll
llvm.amdgcn.raw.buffer.atomic.ll
llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm.amdgcn.raw.buffer.load.format.ll
llvm.amdgcn.raw.buffer.load.ll
llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm.amdgcn.raw.tbuffer.store.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.buffer.load.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sethalt.ll
llvm.amdgcn.s.setreg.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll
llvm.amdgcn.sdot8.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll
llvm.amdgcn.sqrt.f16.ll
llvm.amdgcn.sqrt.ll
llvm.amdgcn.struct.buffer.atomic.fadd.ll
llvm.amdgcn.struct.buffer.atomic.ll
llvm.amdgcn.struct.buffer.load.format.d16.ll
llvm.amdgcn.struct.buffer.load.format.ll
llvm.amdgcn.struct.buffer.load.format.v3f16.ll [AMDGPU] Optimize VGPR LiveRange in waterfall loops 2021-07-13 12:15:08 +02:00
llvm.amdgcn.struct.buffer.load.ll
llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm.amdgcn.struct.buffer.store.format.ll
llvm.amdgcn.struct.buffer.store.ll
llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm.amdgcn.struct.tbuffer.store.ll
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm.amdgcn.tbuffer.load.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll [AMDGPU] Added udot2 op_sel test. NFC. 2021-04-09 12:19:42 -07:00
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.demote.ll [AMDGPU] Fix WQM failure with single block inactive demote 2021-05-06 21:02:26 +09:00
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
llvm.ceil.f16.ll
llvm.cos.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
llvm.fmuladd.f16.ll
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.log10.ll
llvm.log.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.log.ll
llvm.maxnum.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
llvm.memcpy.ll
llvm.minnum.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
llvm.mulo.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.pow-gfx9.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
llvm.pow.ll
llvm.powi.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
llvm.round.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.sin.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
lo16-32bit-physreg-copy.mir
lo16-hi16-illegal-copy.mir
lo16-hi16-physreg-copy.mir
lo16-lo16-physreg-copy-agpr.mir
lo16-lo16-physreg-copy-sgpr.mir
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-global-f32.ll
load-global-f64.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i8.ll
load-local-i16.ll
load-local-i32.ll
load-local-i64.ll
load-local-redundant-copies.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-local.96.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
load-local.128.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
load-select-ptr.ll
load-store-opt-scc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics-fp.ll
local-atomics.ll
local-memory.amdgcn.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
local-memory.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
local-memory.r600.ll
local-stack-alloc-block-sp-reference.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
local-stack-slot-offset.ll
loop_break.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
loop_exit_with_xor.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
loop_header_nopred.mir
loop-address.ll
loop-idiom.ll
loop-live-out-copy-undef-subrange.ll
loop-prefetch.ll
lower-control-flow-other-terminators.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lower-kernargs.ll
lower-kernel-and-module-lds.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-kernel-lds-constexpr.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-kernel-lds-global-uses.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-kernel-lds-super-align.ll [AMDGPU] Check for pointer operand while refining LDS align 2021-06-23 12:27:55 -07:00
lower-kernel-lds.ll [AMDGPU] Disable LDS lowering for GFX shaders 2021-07-20 02:55:25 -07:00
lower-mem-intrinsics-threshold.ll
lower-mem-intrinsics.ll
lower-module-lds-constantexpr.ll [AMDGPU] Use performOptimizedStructLayout for LDS sort 2021-06-22 09:58:10 -07:00
lower-module-lds-global-alias.ll [AMDGPU] Use performOptimizedStructLayout for LDS sort 2021-06-22 09:58:10 -07:00
lower-module-lds-global-uses.ll [AMDGPU] Use performOptimizedStructLayout for LDS sort 2021-06-22 09:58:10 -07:00
lower-module-lds-inactive.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-indirect.ll [AMDGPU] Fix module LDS selection 2021-05-20 15:59:01 -07:00
lower-module-lds-offsets.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-used-list.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-module-lds.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-range-metadata-intrinsic-call.ll
lower-term-opcodes.mir
lshl64-to-32.ll
lshr.v2i16.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
machine-cse-commute-target-flags.mir
machinelicm-convergent.mir
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll AMDGPU: Add missing tests for v_fma_mixlo 2021-06-21 10:58:53 -04:00
mad-mix.ll
mad.u16.ll
madak-inline-constant.mir
madak.ll
madmk.ll
mai-hazards-gfx90a.mir
mai-hazards.mir
mai-inline.ll
max3.ll
max-literals.ll
max-sgprs.ll
max.i16.ll
max.ll
mcp-overlap-after-propagation.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
med3-no-simplify.ll
mem-builtins.ll
memcpy-fixed-align.ll
memcpy-inline-fails.ll
memcpy-scoped-aa.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory_clause.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
memory_clause.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-atomic-insert-end.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-fence.ll [AMDGPU] Update gfx90a memory model support 2021-06-30 04:05:22 +00:00
memory-legalizer-flat-agent.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-flat-nontemporal.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
memory-legalizer-flat-singlethread.ll
memory-legalizer-flat-system.ll [AMDGPU] Update gfx90a memory model support 2021-06-30 04:05:22 +00:00
memory-legalizer-flat-volatile.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-flat-wavefront.ll
memory-legalizer-flat-workgroup.ll [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
memory-legalizer-global-agent.ll
memory-legalizer-global-nontemporal.ll
memory-legalizer-global-singlethread.ll
memory-legalizer-global-system.ll [AMDGPU] Update gfx90a memory model support 2021-06-30 04:05:22 +00:00
memory-legalizer-global-volatile.ll
memory-legalizer-global-wavefront.ll
memory-legalizer-global-workgroup.ll
memory-legalizer-invalid-addrspace.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-invalid-syncscope.ll
memory-legalizer-local-agent.ll
memory-legalizer-local-nontemporal.ll
memory-legalizer-local-singlethread.ll
memory-legalizer-local-system.ll
memory-legalizer-local-volatile.ll
memory-legalizer-local-wavefront.ll
memory-legalizer-local-workgroup.ll
memory-legalizer-local.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-atomics.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-private-nontemporal.ll
memory-legalizer-private-volatile.ll
memory-legalizer-region.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-store-infinite-loop.ll
merge-image-load-gfx10.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-load.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-sample-gfx10.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-sample.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store-agpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store-physreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store-vreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-m0.mir
merge-out-of-order-ldst.ll
merge-out-of-order-ldst.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
merge-tbuffer.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
mesa3d.ll
mesa_regression.ll
mfma-loop.ll
min3.ll
min.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
mir-print-dead-csr-fi.mir
misched-killflags.mir
missing-store.ll
mixed_wave32_wave64.ll
mixed-wave32-wave64.ll
mode-register.mir
move-addr64-rsrc-dead-subreg-writes.ll
move-load-addr-to-valu.mir [AMDGPU] Change FLAT Scratch SADDR to VADDR form in moveToVALU 2021-05-03 10:57:14 -07:00
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
mubuf-legalize-operands.mir [AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP 2021-07-13 12:15:08 +02:00
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
mul24-pass-ordering.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
mul_int24.ll [AMDGPU] Regenerate mul24 test checks 2021-07-25 15:13:09 +01:00
mul_uint24-amdgcn.ll [AMDGPU] Regenerate mul24 test checks 2021-07-25 15:13:09 +01:00
mul_uint24-r600.ll [AMDGPU] Regenerate mul24 test checks 2021-07-25 15:13:09 +01:00
mul.i16.ll
mul.ll
multi-divergent-exit-region.ll [AMDGPU] Don't handle export done when unify exit nodes 2021-07-14 14:54:37 +08:00
multi-dword-vgpr-spill.ll
multilevel-break.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
nand.ll
need-fp-from-csr-vgpr-spill.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
nested-calls.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
nested-loop-conditions.ll
no-bundle-asm.ll
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-remat-indirect-mov.mir
no-shrink-extloads.ll
non-entry-alloca.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
noop-shader-O0.ll
nop-data.ll
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll
nsa-reassign.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
nsa-vmem-hazard.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
nullptr.ll
occupancy-levels.ll
offset-split-flat.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
offset-split-global.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
omod-nsz-flag.mir
omod.ll [AMDGPU] Enable output modifiers for double precision instructions 2021-04-01 10:08:17 -04:00
opencl-image-metadata.ll
opencl-printf-no-hostcall.ll
opencl-printf.ll
operand-folding.ll
operand-spacing.ll
opt_exec_copy_fold.mir
opt-pipeline.ll Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees" 2021-06-24 02:33:50 +01:00
opt-sgpr-to-vgpr-copy.mir
optimize-exec-copies-extra-insts-after-copy.mir
optimize-exec-mask-pre-ra-loop-phi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
optimize-exec-masking-pre-ra.mir
optimize-exec-masking-strip-terminator-bits.mir
optimize-if-exec-masking.mir
optimize-negated-cond-exec-masking-wave32.mir
optimize-negated-cond-exec-masking.mir
optimize-negated-cond.ll
or3.ll
or.ll
pack.v2f16.ll
pack.v2i16.ll
packed-fp32.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
packed-op-sel.ll
packetizer.ll
pal-simple-indirect-call.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
pal-userdata-regs.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll [AMDGPU] Save VGPR of whole wave when spilling 2021-04-12 11:01:38 +02:00
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-build-spill-partial-agpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pei-build-spill.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
pei-reg-scavenger-position.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pei-scavenge-sgpr-carry-out.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pei-scavenge-sgpr-gfx9.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pei-scavenge-sgpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pei-scavenge-vgpr-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
perfhint.ll [AMDGPU] Tune perfhint analysis to account access width 2021-07-21 12:46:10 -07:00
permute.ll
phi-elimination-assertion.mir
phi-elimination-end-cf.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
phi-vgpr-input-moveimm.mir
pk_max_f16_literal.ll
post-ra-sched-kill-bundle-use-inst.mir
post-ra-sched-reset.mir
post-ra-soft-clause-dbg-info.ll
postra-bundle-memops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postra-machine-sink.mir
postra-norename.mir
power-sched-no-instr-sunit.mir
predicate-dp4.ll
predicates.ll
preserve-hi16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
print-mir-custom-pseudo.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll [AMDGPU, test] Fix use of undef FileCheck var 2021-04-08 09:42:59 +01:00
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering. 2021-06-07 18:00:41 +05:30
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
promote-alloca-pointer-array.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-constantexpr-use.ll [AMDGPU] Rename "LDS lowering" pass name. 2021-04-14 20:19:53 +05:30
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
promote-alloca-volatile.ll
promote-constOffset-to-imm-gfx10.mir
promote-constOffset-to-imm-gfx90a.mir AMDGPU: Fix SILoadStoreOptimizer for gfx90a 2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.ll AMDGPU: Fix SILoadStoreOptimizer for gfx90a 2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.mir
promote-vect3-load.ll
propagate-attributes-bitcast-function.ll
propagate-attributes-clone.ll
propagate-attributes-flat-work-group-size.ll
propagate-attributes-function-pointer-argument.ll Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees" 2021-06-24 02:33:50 +01:00
propagate-attributes-single-set.ll
ptr-arg-dbg-value.ll [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs 2021-07-14 04:29:42 -07:00
ptrmask.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll
rcp-pattern.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll [AMDGPU] Add some GFX10.3 testing. NFC. 2021-05-11 11:21:19 +01:00
readlane_exec0.mir
README
reassoc-scalar.ll
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regcoal-subrange-join.mir
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir
regcoalescer-resolve-lane-conflict-by-subranges.mir [RegisterCoalescer] Resolve conflict based on liveness of subregister 2021-07-14 14:43:22 +08:00
regcoalescing-remove-partial-redundancy-assert.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
register-count-comments.ll
rel32.ll
remat-fp64-constants.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
remat-sop.mir [AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization 2021-07-14 13:03:58 -07:00
remat-vop.mir [AMDGPU] Mark relevant rematerializable VOP3 instructions 2021-07-21 14:44:13 -07:00
remove-short-exec-branches-gpr-idx-mode.mir
remove-short-exec-branches-special-instructions.mir
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
replace-lds-by-ptr-call-diamond-shape.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-call-selected_functions.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-global-scope-use.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-inline-asm-call.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-kernel-only-used-lds.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-not-reachable-lds.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-small-lds.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-indirect-call-diamond-shape.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-indirect-call-selected_functions.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-indirect-call-signature-match.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-multiple-lds.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-same-lds.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-within-const-expr1.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-within-const-expr2.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-within-phi-inst.ll Disable ReplaceLDS pass, patch up tests to match 2021-06-26 01:36:42 +01:00
reqd-work-group-size.ll
reserve-vgpr-for-sgpr-spill.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
reserved-reg-in-clause.mir
ret_jump.ll
ret.ll
return-with-successors.mir
returnaddress.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_add_co_pseudo_lowering.mir
s_addk_i32.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
s_code_end.ll
s_movk_i32.ll
s_mulk_i32.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
sad.ll
saddo.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
saddsat.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
salu-to-valu.ll [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions 2021-05-14 10:10:43 +01:00
sampler-resource-id.ll
scalar_to_vector_v2x16.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
scalar_to_vector.ll
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
sched-assert-dead-def-subreg-use-other-subreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sched-assert-onlydbg-value-empty-region.mir
sched-crash-dbg-value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sched-prefer-non-mfma.mir
schedule-barrier-fpmode.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
schedule-barrier.mir
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
schedule-regpressure-limit3.ll
schedule-regpressure-limit-clustering.ll
schedule-regpressure-limit.ll
schedule-regpressure.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
schedule-xdl-resource.ll
scheduler-handle-move-bundle.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
sdiv64.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
sdiv.ll
sdivrem24.ll
sdivrem64.r600.ll
sdwa-gfx9.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-op64-test.ll
sdwa-ops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-peephole-instr-gfx10.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-peephole-instr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-peephole.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
sdwa-preserve.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-scalar-ops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-stack.mir
sdwa-vop2-64bit.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select64.ll
select-constant-cttz.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll
select-opt.ll
select-undef.ll
select-vectors.ll
select.f16.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
set-gpr-idx-peephole.mir [AMDGPU] Remove set_gpr_idx instructions in conditional blocks 2021-04-30 22:15:45 +01:00
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
setcc-opt.ll
setcc-sext.ll
setcc.ll
seto.ll
setuo.ll
sext-divergence-driven-isel.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
sgpr-control-flow.ll [AMDGPU] Add Optimize VGPR LiveRange Pass. 2021-06-21 15:25:55 +08:00
sgpr-copy-duplicate-operand.ll
sgpr-copy-local-cse.ll
sgpr-copy.ll
sgpr-phys-copy.mir
sgpr-regalloc-flags.ll CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis 2021-07-19 21:08:26 -04:00
sgpr-spill-dead-frame-in-dbg-value.mir
sgpr-spill-no-vgprs.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
sgpr-spill-partially-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sgpr-spill-wrong-stack-id.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
sgpr-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
shift-i64-opts.ll
shift-i128.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
shift-select.ll
shl_add_constant.ll
shl_add_ptr_csub.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
shl_add_ptr_global.ll
shl_add_ptr.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
shl_add.ll
shl_or.ll
shl-add-to-add-shl.ll
shl.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
shl.v2i16.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
shrink-add-sub-constant.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
shrink-carry.mir
shrink-instructions-flags.mir
shrink-instructions-illegal-fold.mir
shrink-instructions-implicit-vcclo.mir
shrink-insts-scalar-bit-ops.mir
shrink-vop3-carry-out.mir
si-annotate-cf-kill.ll
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
si-annotate-cfg-loop-assert.ll
si-annotatecfg-multiple-backedges.ll
si-fix-sgpr-copies.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
si-i1-copies.mir
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
si-lower-i1-copies.mir
si-lower-sgpr-spills.mir
si-scheduler.ll
si-sgpr-spill.ll
si-spill-cf.ll
si-spill-sgpr-stack.ll [AMDGPU] Save VGPR of whole wave when spilling 2021-04-12 11:01:38 +02:00
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
sign_extend.ll
simple-indirect-call.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
simplify-libcalls2.ll
simplify-libcalls.ll [amdgpu] Add -enable-ocl-mangling-mismatch-workaround. 2021-06-08 15:42:27 -04:00
simplifydemandedbits-recursion.ll
sink-image-sample.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
skip-branch-taildup-ret.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
skip-branch-trap.ll
skip-if-dead.ll [AMDGPU] Add Optimize VGPR LiveRange Pass. 2021-06-21 15:25:55 +08:00
skip-promote-alloca-vector-users.ll [AMDGPU] Skip promote-alloca for insertelement/insertvalue users 2021-04-30 08:37:26 +05:30
smed3.ll
smem-no-clause-coalesced.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
smem-war-hazard.mir
sminmax.ll
sminmax.v2i16.ll
smrd_vmem_war.ll
smrd-fold-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
smrd-gfx10.ll
smrd-vccz-bug.ll
smrd.ll
soft-clause-dbg-value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
soft-clause-exceeds-register-budget.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
sopk-compares.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
speculative-execution-freecasts.ll
spill192.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill224.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill_more_than_wavesize_csr_sgprs.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
spill-agpr-partially-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill-agpr.ll
spill-agpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
spill-empty-live-interval.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
spill-m0.ll [AMDGPU] Save VGPR of whole wave when spilling 2021-04-12 11:01:38 +02:00
spill-offset-calculation.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
spill-reg-tuple-super-reg-use.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill-scavenge-offset.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
spill-sgpr-csr-live-ins.mir
spill-sgpr-stack-no-sgpr.ll [AMDGPU] Save VGPR of whole wave when spilling 2021-04-12 11:01:38 +02:00
spill-special-sgpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill-vgpr-to-agpr.ll
spill-wide-sgpr.ll
split-arg-dbg-value.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
split-scalar-i64-add.ll
split-smrd.ll
split-vector-memoperand-offsets.ll
splitkit-copy-bundle.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
splitkit-copy-live-lanes.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
splitkit-getsubrangeformask.ll [RegisterCoalescer] Resolve conflict based on liveness of subregister 2021-07-14 14:43:22 +08:00
splitkit-nolivesubranges.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
splitkit.mir
sra.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
sram-ecc-default.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
sramecc-subtarget-feature-any.ll
sramecc-subtarget-feature-disabled.ll
sramecc-subtarget-feature-enabled.ll
srem64.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
srem-seteq-illegal-types.ll Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
srem.ll
srl.ll [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts 2021-05-07 13:12:30 +01:00
sroa-before-unroll.ll
SRSRC-GIT-clobber-check.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ssubo.ll
ssubsat.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
stack-pointer-offset-relative-frameindex.ll
stack-realign-kernel.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
stack-realign.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
stack-size-overflow.ll Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular) 2021-06-22 09:55:20 -07:00
stack-slot-color-sgpr-vgpr-spills.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
stale-livevar-in-twoaddr-pass.mir
store_typed.ll
store-barrier.ll
store-clobbers-load.ll
store-global.ll
store-hi16.ll
store-local.96.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
store-local.128.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
store-local.ll
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
stress-calls.ll
strict_fadd.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
strict_fadd.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fadd.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fma.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
strict_fma.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fma.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fmul.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
strict_fmul.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fmul.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fsub.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
strict_fsub.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fsub.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
structurize1.ll
structurize.ll
sub_i1.ll
sub-zext-cc-zext-cc.ll
sub.i16.ll
sub.ll
sub.v2i16.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
subreg_interference.mir
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir [AMDGPU] Mark relevant rematerializable VOP3 instructions 2021-07-21 14:44:13 -07:00
subreg-undef-def-with-other-subreg-defs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
subvector-test.mir
swdev282079.ll AMDGPU: Fix assert on inline asm on gfx90a 2021-04-23 09:00:25 -04:00
swdev282079.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
switch-default-block-unreachable.ll
switch-unreachable.ll
swizzle-export.ll
syncscopes.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
tail-call-amdgpu-gfx.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
tail-call-cgp.ll
tail-dup-bundle.mir
tail-duplication-convergent.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
tgsplit.ll
tid-code-object-v2-backwards-compatibility.ll AMDGPU: Add gfx90c support to code object v2 for backwards compatibility 2021-04-08 16:42:43 -04:00
tid-mul-func-xnack-all-any.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-not-supported.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-off.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-on.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-1.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-2.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-1.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-2.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-invalid-any-off-on.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-any.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-not-supported.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-off.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-on.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
token-factor-inline-limit-test.ll
transform-block-with-return-to-epilog.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
trap-abis.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store-i64.ll
trunc-store-vec-i16-to-i8.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll
tti-unroll-prefs.ll
twoaddr-fma-f64.mir
twoaddr-fma.mir
twoaddr-mad.mir
uaddo.ll
uaddsat.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
udiv64.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
udiv.ll [DAGCombiner] Add support for mulhi const folding in DAGCombiner 2021-07-05 12:01:26 +01:00
udivrem24.ll
udivrem64.r600.ll
udivrem.ll
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
uitofp.f16.ll
umed3.ll
unaligned-load-store.ll
unallocatable-bundle-regression.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
undef-subreg-use-after-coalesce.mir
undefined-physreg-sgpr-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
undefined-subreg-liverange.ll
unexpected-reg-unit-state.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
uniform-work-group-attribute-missing.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
uniform-work-group-multistep.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
uniform-work-group-nested-function-calls.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
uniform-work-group-prevent-attribute-propagation.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
uniform-work-group-propagate-attribute.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
uniform-work-group-recursion-test.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
uniform-work-group-test.ll [AMDGPU] Deduce attributes with the Attributor 2021-07-24 06:07:15 +03:00
unify-metadata.ll
unigine-liveness-crash.ll
unknown-processor.ll
unpack-half.ll
unroll.ll [AMDGPU][CostModel] Refine cost model for control-flow instructions. 2021-04-10 09:20:24 +03:00
unstructured-cfg-def-use-issue.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
unsupported-calls.ll [AMDGPU] Remove error check for indirect calls and add missing queue-ptr 2021-04-20 00:35:17 +05:30
unsupported-cc.ll
unsupported-image-a16.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unsupported-image-g16.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
update-lds-alignment.ll [AMDGPU] Use performOptimizedStructLayout for LDS sort 2021-06-22 09:58:10 -07:00
update-phi.ll [AMDGPU] Don't handle export done when unify exit nodes 2021-07-14 14:54:37 +08:00
urem64.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
urem-seteq-illegal-types.ll Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
urem.ll
use-sgpr-multiple-times.ll
usubo.ll
usubsat.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
v1i64-kernel-arg.ll
v1024.ll
v_cndmask.ll
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
v_mac.ll
v_madak_f16.ll
v_mov_b64_expand_and_shrink.mir [AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion 2021-07-01 09:00:29 -07:00
v_mov_b64_expansion.mir [AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion 2021-07-01 09:00:29 -07:00
v_pack.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
v_swap_b32.mir [AMDGPU] Fix v_swap_b32 formation on physical registers 2021-04-29 20:53:40 +01:00
valu-i1.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
vccz-corrupt-bug-workaround.mir
vcmpx-exec-war-hazard.mir
vcmpx-permlane-hazard.mir
vector_shuffle.packed.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca-bitcast.ll
vector-alloca-limits.ll
vector-alloca.ll
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-buffer-fat-pointer.ll
vectorize-global-local.ll
vectorize-loads.ll
verify-constant-bus-violations.mir
verify-ds-gws-align.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-duplicate-literal.mir [AMDGPU] Allow multiple uses of the same literal 2021-04-20 16:44:01 +01:00
verify-gfx90a-aligned-vgprs.mir
verify-sop.mir
vertex-fetch-encoding.ll
vgpr-descriptor-waterfall-loop-idom-update.ll [AMDGPU] Optimize VGPR LiveRange in waterfall loops 2021-07-13 12:15:08 +02:00
vgpr-liverange-ir.ll [AMDGPU] Improve killed check for vgpr optimization 2021-07-21 15:24:59 +02:00
vgpr-liverange.ll [AMDGPU] Improve killed check for vgpr optimization 2021-07-21 15:24:59 +02:00
vgpr-remat.mir
vgpr-spill-dead-frame-in-dbg-value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vgpr-spill-emergency-stack-slot-compute.ll
vgpr-spill-emergency-stack-slot.ll
vgpr-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vgpr-tuple-allocation.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
vi-removed-intrinsics.ll
virtregrewrite-undef-identity-copy.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
visit-physreg-vgpr-imm-folding-bug.ll
vmem-to-salu-hazard.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vmem-vcc-hazard.mir
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-agpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-back-edge-loop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-debug.mir [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
waitcnt-flat.ll
waitcnt-loop-irreducible.mir
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll
waitcnt-meta-instructions.mir
waitcnt-no-redundant.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-overflow.mir
waitcnt-permute.mir
waitcnt-preexisting-vscnt.mir [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
waitcnt-preexisting.mir [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 2021-05-11 13:17:33 -07:00
waitcnt-skip-meta.mir
waitcnt-vmem-waw.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-vscnt.ll
waitcnt-vscnt.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wave32.ll Revert rG939291041bb35b8088e3b61be2b8b3bc950f64a7 "[AMDGPU] Regenerate wave32.ll test checks" 2021-07-25 15:59:26 +01:00
wave_dispatch_regs.ll
widen_extending_scalar_loads.ll
widen-smrd-loads.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
widen-vselect-and-mask.ll
wqm.ll
wqm.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
wwm-reserved-spill.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
wwm-reserved.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
xfail.r600.bitcast.ll
xnack-subtarget-feature-any.ll
xnack-subtarget-feature-disabled.ll
xnack-subtarget-feature-enabled.ll
xnor.ll
xor3-i1-const.ll
xor3.ll
xor_add.ll
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.