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e7d64b577c
This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 llvm-svn: 235014
67 lines
1.8 KiB
LLVM
67 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Make sure that we don't crash when legalizing vselect and vsetcc and that
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; we are able to generate vector blend instructions.
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; CHECK-LABEL: simple_widen
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; CHECK-NOT: blend
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; CHECK: ret
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define void @simple_widen() {
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entry:
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%0 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef
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store <2 x float> %0, <2 x float>* undef
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ret void
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}
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; CHECK-LABEL: complex_inreg_work
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; CHECK: blend
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; CHECK: ret
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define void @complex_inreg_work() {
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entry:
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%0 = fcmp oeq <2 x float> undef, undef
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%1 = select <2 x i1> %0, <2 x float> undef, <2 x float> undef
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store <2 x float> %1, <2 x float>* undef
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ret void
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}
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; CHECK-LABEL: zero_test
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; CHECK: xorps %xmm0, %xmm0
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; CHECK: ret
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define void @zero_test() {
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entry:
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%0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer
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store <2 x float> %0, <2 x float>* undef
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ret void
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}
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; CHECK-LABEL: full_test
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; CHECK: blend
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; CHECK: ret
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define void @full_test() {
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entry:
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%Cy300 = alloca <4 x float>
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%Cy11a = alloca <2 x float>
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%Cy118 = alloca <2 x float>
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%Cy119 = alloca <2 x float>
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br label %B1
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B1: ; preds = %entry
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%0 = load <2 x float>, <2 x float>* %Cy119
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%1 = fptosi <2 x float> %0 to <2 x i32>
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%2 = sitofp <2 x i32> %1 to <2 x float>
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%3 = fcmp ogt <2 x float> %0, zeroinitializer
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%4 = fadd <2 x float> %2, <float 1.000000e+00, float 1.000000e+00>
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%5 = select <2 x i1> %3, <2 x float> %4, <2 x float> %2
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%6 = fcmp oeq <2 x float> %2, %0
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%7 = select <2 x i1> %6, <2 x float> %0, <2 x float> %5
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store <2 x float> %7, <2 x float>* %Cy118
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%8 = load <2 x float>, <2 x float>* %Cy118
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store <2 x float> %8, <2 x float>* %Cy11a
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ret void
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}
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