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bc658bf60a
This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
47 lines
1.4 KiB
LLVM
47 lines
1.4 KiB
LLVM
; Test negated floating-point absolute on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test f32.
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declare float @llvm.fabs.f32(float %f)
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define float @f1(float %f) {
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; CHECK-LABEL: f1:
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; CHECK: lndfr %f0, %f0
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; CHECK: br %r14
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%abs = call float @llvm.fabs.f32(float %f)
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%res = fsub float -0.0, %abs
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ret float %res
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}
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; Test f64.
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declare double @llvm.fabs.f64(double %f)
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define double @f2(double %f) {
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; CHECK-LABEL: f2:
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; CHECK: lndfr %f0, %f0
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; CHECK: br %r14
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%abs = call double @llvm.fabs.f64(double %f)
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%res = fsub double -0.0, %abs
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ret double %res
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}
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; Test f128. With the loads and stores, a pure negative-absolute would
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; probably be better implemented using an OI on the upper byte. Do some
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; extra processing so that using FPRs is unequivocally better.
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declare fp128 @llvm.fabs.f128(fp128 %f)
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define void @f3(fp128 *%ptr, fp128 *%ptr2) {
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; CHECK-LABEL: f3:
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; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
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; CHECK-DAG: wflnxb [[NEGREG1:%v[0-9]+]], [[REG1]]
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; CHECK: wfdxb [[RES:%v[0-9]+]], [[NEGREG1]], [[REG2]]
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; CHECK: vst [[RES]], 0(%r2)
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; CHECK: br %r14
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%orig = load fp128 , fp128 *%ptr
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%abs = call fp128 @llvm.fabs.f128(fp128 %orig)
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%negabs = fsub fp128 0xL00000000000000008000000000000000, %abs
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%op2 = load fp128 , fp128 *%ptr2
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%res = fdiv fp128 %negabs, %op2
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store fp128 %res, fp128 *%ptr
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ret void
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}
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