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e43ad0c5d9
The SystemZ back-end uses a sequence of IPM followed by arithmetic operations to implement the SETCC primitive. This is currently done early during SelectionDAG. This patch moves generating those sequences to much later in SelectionDAG (during PreprocessISelDAG). This doesn't change much in generated code by itself, but it allows further enhancements that will be checked-in as follow-on commits. llvm-svn: 322987
74 lines
1.8 KiB
LLVM
74 lines
1.8 KiB
LLVM
; Test SETCC with an i32 result for every integer condition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Test CC in { 0 }, with 3 don't care.
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define i64 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], -268435456
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; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%cond = icmp eq i32 %a, %b
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%res = zext i1 %cond to i64
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ret i64 %res
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}
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; Test CC in { 1 }, with 3 don't care.
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define i64 @f2(i32 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
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; CHECK: br %r14
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%cond = icmp slt i32 %a, %b
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%res = zext i1 %cond to i64
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ret i64 %res
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}
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; Test CC in { 0, 1 }, with 3 don't care.
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define i64 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], -536870912
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; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%cond = icmp sle i32 %a, %b
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%res = zext i1 %cond to i64
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ret i64 %res
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}
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; Test CC in { 2 }, with 3 don't care.
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define i64 @f4(i32 %a, i32 %b) {
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; CHECK-LABEL: f4:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%cond = icmp sgt i32 %a, %b
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%res = zext i1 %cond to i64
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ret i64 %res
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}
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; Test CC in { 0, 2 }, with 3 don't care.
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define i64 @f5(i32 %a, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: xilf [[REG]], 4294967295
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; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
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; CHECK: br %r14
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%cond = icmp sge i32 %a, %b
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%res = zext i1 %cond to i64
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ret i64 %res
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}
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; Test CC in { 1, 2 }, with 3 don't care.
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define i64 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], 1879048192
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; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%cond = icmp ne i32 %a, %b
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%res = zext i1 %cond to i64
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ret i64 %res
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}
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