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407c9d3378
When combiner AA is enabled, look at stores on the same chain. Non-aliasing stores are moved to the same chain so the existing code fails because it expects to find an adajcent store on a consecutive chain. Because of how DAGCombiner tries these store combines, MergeConsecutiveStores doesn't see the correct set of stores on the chain when it visits the other stores. Each store individually has its chain fixed before trying to merge consecutive stores, and then tries to merge stores from that point before the other stores have been processed to have their chains fixed. To fix this, attempt to use FindBetterChain on any possibly neighboring stores in visitSTORE. Suppose you have 4 32-bit stores that should be merged into 1 vector store. One store would be visited first, fixing the chain. What happens is because not all of the store chains have yet been fixed, 2 of the stores are merged. The other 2 stores later have their chains fixed, but because the other stores were already merged, they have different memory types and merging the two different sized stores is not supported and would be more difficult to handle. llvm-svn: 246307
35 lines
1.2 KiB
LLVM
35 lines
1.2 KiB
LLVM
; Test the handling of unnamed short vector arguments.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
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; This routine is called with two named vector argument (passed
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; in %v24 and %v26) and two unnamed vector arguments (passed
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; in the single-wide stack slots at 160 and 168).
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declare void @bar(<4 x i8>, <4 x i8>, ...)
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define void @foo() {
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; CHECK-VEC-LABEL: foo:
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; CHECK-VEC-DAG: vrepib %v24, 1
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; CHECK-VEC-DAG: vrepib %v26, 2
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; CHECK-VEC: brasl %r14, bar@PLT
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;
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; CHECK-STACK: .LCPI0_0:
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; CHECK-STACK: .quad 217020518463700992 # 0x303030300000000
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; CHECK-STACK: .quad 289360691284934656 # 0x404040400000000
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; CHECK-STACK-LABEL: foo:
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; CHECK-STACK: aghi %r15, -176
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; CHECK-STACK-DAG: larl [[REG1:%r[0-9]+]], .LCPI0_0
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; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
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; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
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; CHECK-STACK: brasl %r14, bar@PLT
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call void (<4 x i8>, <4 x i8>, ...) @bar
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(<4 x i8> <i8 1, i8 1, i8 1, i8 1>,
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<4 x i8> <i8 2, i8 2, i8 2, i8 2>,
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<4 x i8> <i8 3, i8 3, i8 3, i8 3>,
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<4 x i8> <i8 4, i8 4, i8 4, i8 4>)
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ret void
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}
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