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c0d659ef28
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134
115 lines
3.1 KiB
LLVM
115 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
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declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1(
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i32);
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define <vscale x 1 x i1> @intrinsic_vmclr_m_pseudo_nxv1i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1(
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i32 %0)
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ret <vscale x 1 x i1> %a
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}
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declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1(
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i32);
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define <vscale x 2 x i1> @intrinsic_vmclr_m_pseudo_nxv2i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1(
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i32 %0)
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ret <vscale x 2 x i1> %a
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}
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declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1(
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i32);
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define <vscale x 4 x i1> @intrinsic_vmclr_m_pseudo_nxv4i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1(
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i32 %0)
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ret <vscale x 4 x i1> %a
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}
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declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1(
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i32);
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define <vscale x 8 x i1> @intrinsic_vmclr_m_pseudo_nxv8i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1(
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i32 %0)
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ret <vscale x 8 x i1> %a
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}
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declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1(
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i32);
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define <vscale x 16 x i1> @intrinsic_vmclr_m_pseudo_nxv16i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1(
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i32 %0)
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ret <vscale x 16 x i1> %a
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}
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declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1(
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i32);
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define <vscale x 32 x i1> @intrinsic_vmclr_m_pseudo_nxv32i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1(
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i32 %0)
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ret <vscale x 32 x i1> %a
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}
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declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1(
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i32);
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define <vscale x 64 x i1> @intrinsic_vmclr_m_pseudo_nxv64i1(i32 %0) nounwind {
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; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1(
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i32 %0)
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ret <vscale x 64 x i1> %a
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}
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