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llvm-mirror/test/CodeGen/RISCV/rvv
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Fraser Cormack ebfa93d23f [RISCV] Fix crash when inserting large fixed-length subvectors 
This patch addresses a compiler crash resulting from passing a
fixed-length type to one that expects scalable vector types. An
assertion was added to prevent this regressing in the future.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97868
2021-03-04 09:27:16 +00:00
..
access-fixed-objects-by-rvv.ll
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
add-vsetvli-gpr.mir
[RISCV] Make LMUL field in VTYPE continuous.
2021-01-22 00:47:32 +08:00
add-vsetvli-vlmax.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
allocate-lmul-2-4-8.ll
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
cleanup-vsetivli.mir
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
cleanup-vsetvli.mir
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
extract-subvector.ll
[RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types
2021-03-01 11:51:05 +00:00
extractelt-fp-rv32.ll
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
2021-02-25 07:51:19 -08:00
extractelt-fp-rv64.ll
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
2021-02-25 07:51:19 -08:00
extractelt-int-rv32.ll
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
2021-02-25 07:51:19 -08:00
extractelt-int-rv64.ll
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
2021-02-25 07:51:19 -08:00
fixed-vectors-extract-subvector.ll
[RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types
2021-03-01 11:51:05 +00:00
fixed-vectors-extract.ll
[RISCV] Add test cases for fixed vector extract element with non-constant index. NFC
2021-02-25 22:36:38 -08:00
fixed-vectors-fp2i.ll
[RISCV] Lower CONCAT_VECTORS to INSERT_SUBVECTOR nodes
2021-03-02 11:13:59 +00:00
fixed-vectors-fp-buildvec.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-fp-conv.ll
[RISCV] Support fixed-length vector FP_ROUND & FP_EXTEND
2021-02-25 12:16:06 +00:00
fixed-vectors-fp-setcc.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-fp-splat.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-fp-vrgather.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-fp.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-i2fp.ll
[RISCV] Support fixed-length vector i2fp/fp2i conversions
2021-02-25 13:47:58 +00:00
fixed-vectors-insert-subvector.ll
[LegalizeVectorTypes] Improve SplitVecRes_INSERT_SUBVECTOR to handle subvector being in the high half of the split or not at element 0 of the low half.
2021-03-02 21:14:13 -08:00
fixed-vectors-insert.ll
[RISCV] Preserve fixed-length VL on insert_vector_elt in more cases
2021-03-04 09:21:10 +00:00
fixed-vectors-int-buildvec.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-int-exttrunc.ll
[RISCV] Lower CONCAT_VECTORS to INSERT_SUBVECTOR nodes
2021-03-02 11:13:59 +00:00
fixed-vectors-int-setcc.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-int-splat-rv32.ll
[RISCV] Fix crash when inserting large fixed-length subvectors
2021-03-04 09:27:16 +00:00
fixed-vectors-int-splat-rv64.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-int-vrgather.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-int.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-mask-load-store.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-mask-logic.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-mask-splat.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
fixed-vectors-vselect.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00
frameindex-addr.ll
[RISCV] Call SelectBaseAddr on the base pointer in the custom isel for vector loads and stores.
2021-02-26 11:38:23 -08:00
insert-subvector.ll
[RISCV] Support INSERT_SUBVECTOR on vector masks
2021-03-01 12:04:11 +00:00
insertelt-fp-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
insertelt-fp-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
insertelt-int-rv32.ll
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
2021-01-25 22:03:52 +00:00
insertelt-int-rv64.ll
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
2021-01-25 22:03:52 +00:00
load-add-store-8.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
load-add-store-16.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
load-add-store-32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
load-add-store-64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
load-mask.ll
[RISCV] Load/store vector mask types.
2021-02-03 13:44:15 +08:00
localvar.ll
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
mask-exts-truncs-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
mask-exts-truncs-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
mask-reg-alloc.mir
[RISCV] Improve register allocation around vector masks
2021-02-20 14:47:51 +00:00
memory-args.ll
[RISCV] Frame handling for RISC-V V extension.
2021-02-17 14:05:19 +08:00
rv32-spill-vector-csr.ll
[RISCV] Spilling for RISC-V V extension. (2nd version)
2021-02-17 14:05:19 +08:00
rv32-spill-vector.ll
[RISCV] Spilling for RISC-V V extension. (2nd version)
2021-02-17 14:05:19 +08:00
rv32-vsetvli-intrinsics.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
rv64-spill-vector-csr.ll
[RISCV] Spilling for RISC-V V extension. (2nd version)
2021-02-17 14:05:19 +08:00
rv64-spill-vector.ll
[RISCV] Spilling for RISC-V V extension. (2nd version)
2021-02-17 14:05:19 +08:00
rv64-vsetvli-intrinsics.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
rvv-vscale.i32.ll
[RISCV] Custom lower ISD::VSCALE.
2021-01-13 17:14:49 -08:00
rvv-vscale.i64.ll
[RISCV] Custom lower ISD::VSCALE.
2021-01-13 17:14:49 -08:00
saddo-sdnode.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
setcc-fp-rv32.ll
[RISCV] Add a pattern for a scalable vector mask vnot.
2021-02-11 15:34:58 -08:00
setcc-fp-rv64.ll
[RISCV] Add a pattern for a scalable vector mask vnot.
2021-02-11 15:34:58 -08:00
setcc-integer-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
setcc-integer-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vaadd-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vaadd-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vaaddu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vaaddu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vadc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadd-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vadd-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vadd-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadd-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomaxu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomaxu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamominu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamominu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoswap-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoswap-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vand-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vand-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vand-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vand-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vasub-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vasub-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vasubu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vasubu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vcompress-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vcompress-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vdiv-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vdiv-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vdiv-sdnode-rv32.ll
[RISCV] Fix incorrect RVV sdiv/udiv lowering
2021-02-02 18:35:53 +00:00
vdiv-sdnode-rv64.ll
[RISCV] Fix incorrect RVV sdiv/udiv lowering
2021-02-02 18:35:53 +00:00
vdivu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vdivu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vdivu-sdnode-rv32.ll
[RISCV] Fix incorrect RVV sdiv/udiv lowering
2021-02-02 18:35:53 +00:00
vdivu-sdnode-rv64.ll
[RISCV] Fix incorrect RVV sdiv/udiv lowering
2021-02-02 18:35:53 +00:00
vexts-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vexts-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfabs-sdnode.ll
[RISCV] Add patterns for scalable-vector fabs & fcopysign
2021-02-16 10:21:09 +00:00
vfadd-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfadd-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfadd-sdnode.ll
[RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.
2021-01-29 17:32:08 -08:00
vfclass-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfclass-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcopysign-sdnode.ll
[RISCV] Add patterns for scalable-vector fabs & fcopysign
2021-02-16 10:21:09 +00:00
vfcvt-f-x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-xu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-xu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfdiv-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfdiv-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfdiv-sdnode.ll
[RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.
2021-01-29 17:32:08 -08:00
vfirst-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfirst-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmadd-sdnode.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmax-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmax-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmerge-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmerge-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmin-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmin-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsub-sdnode.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmul-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmul-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfmul-sdnode.ll
[RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.
2021-01-29 17:32:08 -08:00
vfmv.f.s.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.s.f-rv32.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.s.f-rv64.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.v.f-rv32.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.v.f-rv64.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfncvt-f-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-xu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-xu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rod-f-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rod-f-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfneg-sdnode.ll
[RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.
2021-01-29 17:32:08 -08:00
vfnmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmadd-sdnode.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfnmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsub-sdnode.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfpext-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vfptoi-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vfptrunc-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vfrdiv-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrdiv-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrec7-rv32.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vfrec7-rv64.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vfredmax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredosum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredosum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrsqrt7-rv32.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vfrsqrt7-rv64.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vfrsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnj-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsgnj-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsgnjn-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsgnjn-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsgnjx-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsgnjx-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfslide1down-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1down-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1up-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1up-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsqrt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsqrt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsqrt-sdnode.ll
[RISCV] Add patterns for scalable-vector fsqrt
2021-02-05 09:39:19 +00:00
vfsub-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsub-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfsub-sdnode.ll
[RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines.
2021-01-29 17:32:08 -08:00
vfwadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwadd.w-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfwadd.w-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfwcvt-f-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-xu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-xu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredosum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredosum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub.w-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vfwsub.w-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vid-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vid-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
viota-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
viota-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vitofp-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vle1-rv32.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vle1-rv64.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vle-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vle-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vleff-rv32.ll
[RISCV] Add a VL output to vleff intrinsics.
2021-01-21 17:19:58 -08:00
vleff-rv64.ll
[RISCV] Add a VL output to vleff intrinsics.
2021-01-21 17:19:58 -08:00
vloxei-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vloxei-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vloxseg-rv32.ll
[RISCV] Remove redundant test cases for index segment load (1/8).
2021-02-19 11:56:08 +08:00
vloxseg-rv64.ll
[RISCV] Remove redundant test cases for index segment load (2/8).
2021-02-19 11:56:08 +08:00
vlse-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlse-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlsegff-rv32-dead.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsegff-rv32.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsegff-rv64-dead.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsegff-rv64.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlsseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vluxei-rv32.ll
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0
2021-01-21 18:38:49 -08:00
vluxei-rv64.ll
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0
2021-01-21 18:38:49 -08:00
vluxseg-rv32.ll
[RISCV] Remove redundant test cases for index segment load (3/8).
2021-02-19 11:56:08 +08:00
vluxseg-rv64.ll
[RISCV] Remove redundant test cases for index segment load (4/8).
2021-02-19 11:56:08 +08:00
vmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc.carry.in-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc.carry.in-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmandnot-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmandnot-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmarith-sdnode.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmax-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmax-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmax-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmax-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmaxu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmaxu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmaxu-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmaxu-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmclr-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmclr-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmerge-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmerge-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfeq-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfeq-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfge-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfge-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfgt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfgt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfle-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfle-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmflt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmflt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfne-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfne-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmin-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmin-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmin-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmin-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vminu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vminu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vminu-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vminu-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmornot-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmornot-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc.borrow.in-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc.borrow.in-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbf-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbf-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmseq-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmseq-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmset-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmset-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgtu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgtu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsif-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsif-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsle-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsle-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsleu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsleu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmslt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmslt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsltu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsltu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsne-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsne-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsof-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsof-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmul-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmul-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmul-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmul-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulh-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmulh-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmulh-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vmulhsu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmulhsu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmulhu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmulhu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vmv.s.x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.s.x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.v-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.v-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.x.s-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.x.s-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxnor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxnor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclip-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclip-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclipu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclipu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsra-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsra-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsrl-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsrl-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vor-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vor-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vor-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vor-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vpopc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vpopc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmaxu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmaxu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredminu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredminu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vreductions-fp-sdnode.ll
[RISCV] Support the scalable-vector fadd reduction intrinsic
2021-02-08 09:52:27 +00:00
vreductions-int-rv32.ll
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
2021-02-25 07:51:19 -08:00
vreductions-int-rv64.ll
[RISCV] Support scalable-vector integer reduction intrinsics
2021-02-05 10:10:08 +00:00
vredxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrem-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vrem-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vrem-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vrem-sdnode-rv64.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vremu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vremu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vremu-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vremu-sdnode-rv64.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vrgather-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vrgather-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vrgatherei16-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vrgatherei16-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vrsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrsub-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrsub-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsadd-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsadd-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsaddu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsaddu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsbc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsbc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vse1-rv32.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vse1-rv64.ll
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
vse-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vse-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vselect-fp-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vselect-fp-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vselect-int-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vselect-int-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsext-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsext-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vshl-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vshl-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1down-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1down-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1up-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1up-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslidedown-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslidedown-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslideup-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslideup-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsll-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsll-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsmul-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsmul-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsoxei-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsoxei-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsoxseg-rv32.ll
[RISCV] Remove redundant test cases for index segment store (5/8).
2021-02-19 11:56:08 +08:00
vsoxseg-rv64.ll
[RISCV] Remove redundant test cases for index segment store (6/8).
2021-02-19 11:56:08 +08:00
vsplats-fp.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vsplats-i1.ll
[RISCV] Add vector mask arithmetic ISel patterns
2021-01-07 09:43:25 +00:00
vsplats-i64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsra-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsra-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsra-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsra-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsrl-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsrl-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsrl-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsrl-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsse-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsse-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssra-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssra-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssrl-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssrl-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssub-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssub-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssubu-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vssubu-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsub-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsub-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vsub-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsub-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsuxei-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsuxei-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsuxseg-rv32.ll
[RISCV] Remove redundant test cases for index segment store (7/8).
2021-02-19 11:56:08 +08:00
vsuxseg-rv64.ll
[RISCV] Remove redundant test cases for index segment store (8/8).
2021-02-19 11:56:08 +08:00
vtruncs-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vtruncs-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd.w-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwadd.w-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwaddu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwaddu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwaddu.w-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwaddu.w-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccsu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccsu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccus-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccus-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulsu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulsu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsumu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsumu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub.w-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwsub.w-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwsubu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsubu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsubu.w-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vwsubu.w-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vxor-rv32.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vxor-rv64.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
vxor-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vxor-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vzext-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vzext-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
zvlsseg-zero-vl.ll
[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.
2021-02-24 16:07:33 -08:00