1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
llvm-mirror/test/CodeGen/X86/implicit-use-spill.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

23 lines
779 B
YAML

# RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s | FileCheck %s
# Make sure we don't assert when we try to reload a value that is just implicitly used.
---
# CHECK: name: foo
# This test forces a spill of %0.
name: foo
registers:
- { id: 0, class: gr64 }
body: |
bb.0:
; CHECK: NOOP implicit-def [[VAL:%[0-9]+]]
; VAL should be spilled before csr_noregs, i.e., before we clobber all the registers
; CHECK-NEXT: MOV64mr [[SLOT:%stack.[0-9]+]], 1, $noreg, 0, $noreg, [[VAL]]
; CHECK-NEXT: NOOP csr_noregs
; We need to reload before the (implicit) use.
; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]]:gr64 = MOV64rm [[SLOT]], 1, $noreg, 0, $noreg
; CHECK-NEXT: NOOP implicit [[RELOADED_VAL]]
NOOP implicit-def %0
NOOP csr_noregs
NOOP implicit %0
...