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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
llvm-mirror/test/CodeGen
2010-06-19 01:01:32 +00:00
..
Alpha
ARM Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 2010-06-19 01:01:32 +00:00
Blackfin
CBackend
CellSPU Fix SPU to cope with vector insertelement to an undef position. 2010-06-09 09:58:17 +00:00
CPP
Generic Remove arm_apcscc from the test files. It is the default and doing this 2010-06-17 15:18:27 +00:00
MBlaze
Mips
MSP430
PIC16
PowerPC Remove the local register allocator. 2010-06-15 21:58:33 +00:00
SPARC
SystemZ
Thumb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 2010-06-19 01:01:32 +00:00
Thumb2 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 2010-06-19 01:01:32 +00:00
X86 Don't maintain a set of deleted nodes; instead, use a HandleSDNode 2010-06-18 01:24:29 +00:00
XCore