Vedant Kumar d61070716c Mark @llvm.trap cold ...

A call to @llvm.trap can be expected to be cold (i.e. unlikely to be
reached in a normal program execution).

Outlining paths which unconditionally trap is an important memory
saving. As the hot/cold splitting pass (imho) should not treat all
noreturn calls as cold, explicitly mark @llvm.trap cold so that it can
be outlined.

Split out of https://reviews.llvm.org/D54244.

Differential Revision: https://reviews.llvm.org/D54329

llvm-svn: 346885

2018-11-14 19:53:41 +00:00

..

AsmMatcherEmitter.cpp

Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC

2018-10-19 06:12:02 +00:00

AsmWriterEmitter.cpp

[TableGen] Prevent double flattening of InstAlias asm strings in the asm matcher emitter.

2018-06-18 01:28:01 +00:00

AsmWriterInst.cpp

…

AsmWriterInst.h

…

Attributes.cpp

Remove redundant includes from utils/TableGen.

2017-12-13 21:31:13 +00:00

CallingConvEmitter.cpp

[TableGen] Simplify CallingConvEmitter.cpp. NFC.

2017-10-16 14:52:26 +00:00

CMakeLists.txt

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

CodeEmitterGen.cpp

[tablegen] Avoid creating a temporary vector in getInstructionCase

2017-07-04 06:16:53 +00:00

CodeGenDAGPatterns.cpp

TableGen/CodeGenDAGPatterns: addPredicateFn only once

2018-10-08 16:53:31 +00:00

CodeGenDAGPatterns.h

TableGen/CodeGenDAGPatterns: addPredicateFn only once

2018-10-08 16:53:31 +00:00

CodeGenHwModes.cpp

TableGen support for parameterized register class information

2017-09-14 16:56:21 +00:00

CodeGenHwModes.h

TableGen support for parameterized register class information

2017-09-14 16:56:21 +00:00

CodeGenInstruction.cpp

[WebAssembly] Add isEHScopeReturn instruction property

2018-08-21 19:44:11 +00:00

CodeGenInstruction.h

[WebAssembly] Add isEHScopeReturn instruction property

2018-08-21 19:44:11 +00:00

CodeGenIntrinsics.h

Mark @llvm.trap cold

2018-11-14 19:53:41 +00:00

CodeGenMapTable.cpp

[mips] Improve diagnostics for instruction mapping

2018-01-08 16:25:40 +00:00

CodeGenRegisters.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

CodeGenRegisters.h

[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum

2018-08-16 15:29:24 +00:00

CodeGenSchedule.cpp

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

CodeGenSchedule.h

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

CodeGenTarget.cpp

Mark @llvm.trap cold

2018-11-14 19:53:41 +00:00

CodeGenTarget.h

[GlobalISel][Tablegen] Assign small opcodes to pseudos

2018-05-23 22:10:21 +00:00

CTagsEmitter.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

DAGISelEmitter.cpp

[TableGen] Support multi-alternative pattern fragments

2018-07-13 13:18:00 +00:00

DAGISelMatcher.cpp

Remove redundant includes from utils/TableGen.

2017-12-13 21:31:13 +00:00

DAGISelMatcher.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

DAGISelMatcherEmitter.cpp

[SelectionDAG] Add a isel matcher op to check the type of node results other than result 0.

2017-11-22 07:11:01 +00:00

DAGISelMatcherGen.cpp

[TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum

2018-08-16 15:29:24 +00:00

DAGISelMatcherOpt.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

DFAPacketizerEmitter.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

DisassemblerEmitter.cpp

[WebAssembly] Initial Disassembler.

2018-05-10 22:16:44 +00:00

ExegesisEmitter.cpp

[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.

2018-11-09 13:15:32 +00:00

FastISelEmitter.cpp

Use the container form llvm::sort(C, ...)

2018-09-30 22:31:29 +00:00

FixedLenDecoderEmitter.cpp

Fix MSVC build by correcting placement of declspec after r345056

2018-10-23 17:41:39 +00:00

GlobalISelEmitter.cpp

Use the container form llvm::sort(C, ...)

2018-09-30 22:31:29 +00:00

InfoByHwMode.cpp

llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)

2018-09-27 02:13:45 +00:00

InfoByHwMode.h

[TableGen] Don't separately search for DefaultMode when we're going to iterate the set anyway. NFCI.

2018-08-17 17:45:15 +00:00

InstrDocsEmitter.cpp

[WebAssembly] Add isEHScopeReturn instruction property

2018-08-21 19:44:11 +00:00

InstrInfoEmitter.cpp

[tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands.

2018-10-31 12:28:05 +00:00

IntrinsicEmitter.cpp

Mark @llvm.trap cold

2018-11-14 19:53:41 +00:00

LLVMBuild.txt

Add missing dependency (headers are included from MC, so a link dependency could exist easily enough)

2018-03-29 00:29:43 +00:00

OptParserEmitter.cpp

[Bash-autocompletion] Add support for -std=

2017-08-29 02:01:56 +00:00

PredicateExpander.cpp

[tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands.

2018-10-31 12:28:05 +00:00

PredicateExpander.h

[tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands.

2018-10-31 12:28:05 +00:00

PseudoLoweringEmitter.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

RegisterBankEmitter.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

RegisterInfoEmitter.cpp

Use the container form llvm::sort(C)

2018-10-31 00:31:06 +00:00

RISCVCompressInstEmitter.cpp

Rename DEBUG macro to LLVM_DEBUG.

2018-05-14 12:53:11 +00:00

SDNodeProperties.cpp

TableGen: Allow setting SDNodeProperties on intrinsics

2017-12-20 19:36:28 +00:00

SDNodeProperties.h

TableGen: Allow setting SDNodeProperties on intrinsics

2017-12-20 19:36:28 +00:00

SearchableTableEmitter.cpp

TableGen: Fix ASAN error

2018-10-31 17:46:21 +00:00

SequenceToOffsetTable.h

Remove usages of deprecated std::unary_function and std::binary_function.

2017-09-14 18:33:25 +00:00

SubtargetEmitter.cpp

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

SubtargetFeatureInfo.cpp

IWYU for llvm-config.h in llvm, additions.

2018-04-30 14:59:11 +00:00

SubtargetFeatureInfo.h

Remove \brief commands from doxygen comments.

2018-05-01 15:54:18 +00:00

TableGen.cpp

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

TableGenBackends.h

[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

2018-10-25 07:44:01 +00:00

tdtags

…

Types.cpp

[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.

2017-04-21 15:59:56 +00:00

Types.h

Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.

2016-11-19 13:05:44 +00:00

WebAssemblyDisassemblerEmitter.cpp

[WebAssembly] Read prefixed opcodes as ULEB128s

2018-11-09 01:57:00 +00:00

WebAssemblyDisassemblerEmitter.h

[WebAssembly] Initial Disassembler.

2018-05-10 22:16:44 +00:00

X86DisassemblerShared.h

[X86] Use unique_ptr to simplify memory management. NFC

2018-03-24 07:15:47 +00:00

X86DisassemblerTables.cpp

[X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode.

2018-04-22 00:52:02 +00:00

X86DisassemblerTables.h

[X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute.

2018-03-24 07:48:54 +00:00

X86EVEX2VEXTablesEmitter.cpp

[X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter.

2018-06-19 04:24:44 +00:00

X86FoldTablesEmitter.cpp

[X86] More additions to the load folding tables based on the autogenerated tables.

2018-06-16 23:25:50 +00:00

X86ModRMFilters.cpp

…

X86ModRMFilters.h

Test commit: remove trailing whitespace

2018-09-11 17:28:43 +00:00

X86RecognizableInstr.cpp

[X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.

2018-08-13 22:06:28 +00:00

X86RecognizableInstr.h

[X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0.

2018-06-19 04:24:42 +00:00