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4b6f06420e
The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
133 lines
3.8 KiB
LLVM
133 lines
3.8 KiB
LLVM
; Test 8-bit atomic additions.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
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; Check addition of a variable.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK.
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; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
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; before being used. This shift is independent of the other loop prologue
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; instructions.
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define i8 @f1(i8 *%src, i8 %b) {
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; CHECK-LABEL: f1:
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; CHECK: risbg %r1, %r2, 0, 189, 0{{$}}
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; CHECK-DAG: sll [[SHIFT:%r[0-9]+]], 3
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; CHECK-DAG: l [[OLD:%r[0-9]+]], 0(%r1)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: ar [[ROT]], %r3
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0(%r1)
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; CHECK: jl [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f1:
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; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f1:
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; CHECK-SHIFT2: sll %r3, 24
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw add i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check the minimum signed value. We add 0x80000000 to the rotated word.
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define i8 @f2(i8 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK-DAG: sll %r2, 3
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; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
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; CHECK: afi [[ROT]], -2147483648
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
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; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
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; CHECK: jl [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f2:
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; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f2:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw add i8 *%src, i8 -128 seq_cst
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ret i8 %res
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}
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; Check addition of -1. We add 0xff000000 to the rotated word.
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define i8 @f3(i8 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: afi [[ROT]], -16777216
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f3:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f3:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw add i8 *%src, i8 -1 seq_cst
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ret i8 %res
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}
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; Check addition of 1. We add 0x01000000 to the rotated word.
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define i8 @f4(i8 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: afi [[ROT]], 16777216
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f4:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f4:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw add i8 *%src, i8 1 seq_cst
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ret i8 %res
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}
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; Check the maximum signed value. We add 0x7f000000 to the rotated word.
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define i8 @f5(i8 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: afi [[ROT]], 2130706432
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f5:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f5:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw add i8 *%src, i8 127 seq_cst
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ret i8 %res
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}
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; Check addition of a large unsigned value. We add 0xfe000000 to the
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; rotated word, expressed as a negative AFI operand.
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define i8 @f6(i8 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: afi [[ROT]], -33554432
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f6:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f6:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw add i8 *%src, i8 254 seq_cst
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ret i8 %res
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}
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