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The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers, defined by separate extension specifications (ETM and ETE, respectively), yet they use the same encoding in MSR/MRS. When performing a system register lookup by encoding, we would essentially return a random one, depending on the number, relative position in the TableGen file, whether the TableGen records for system registers are named or not, and, if they are named, depending on record (not register!) name as well. This patch works around the issue by explictly checking for the TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR. Differential Revision: https://reviews.llvm.org/D74074
34 lines
1.2 KiB
ArmAsm
34 lines
1.2 KiB
ArmAsm
// ETE System registers
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//
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// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
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// Read from system register
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mrs x0, TRCRSR
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mrs x0, TRCEXTINSELR
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mrs x0, TRCEXTINSELR0
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mrs x0, TRCEXTINSELR1
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mrs x0, TRCEXTINSELR2
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mrs x0, TRCEXTINSELR3
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// CHECK: mrs x0, TRCRSR // encoding: [0x00,0x0a,0x31,0xd5]
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// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5]
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// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5]
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// CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5]
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// CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5]
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// CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5]
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// Write to system register
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msr TRCRSR, x0
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msr TRCEXTINSELR, x0
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msr TRCEXTINSELR0, x0
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msr TRCEXTINSELR1, x0
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msr TRCEXTINSELR2, x0
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msr TRCEXTINSELR3, x0
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// CHECK: msr TRCRSR, x0 // encoding: [0x00,0x0a,0x11,0xd5]
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// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5]
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// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5]
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// CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5]
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// CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5]
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// CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5]
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