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llvm-mirror/test/MC/ARM/armv8a-fpmul-error.s

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[ARM/AArch64] Support FP16 +fp16fml instructions Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
2018-08-17 13:29:49 +02:00
// RUN: not llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
VFMAL.F16 D0, S1, S2[2]
vfmsl.f16 d0, s1, s2[2]
vfmsl.f16 d0, s1, s2[-1]
vfmal.f16 q0, d1, d2[4]
VFMSL.F16 Q0, D1, D2[4]
vfmal.f16 q0, d1, d2[-1]
[ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operand The indexed variant of vfmal.f16 and vfmsl.f16 instructions use the uppser bits of the indexed operand to store the index (1 bit for the double variant, 2 bits for the quad). This limits the usable registers to d0 - d7 or s0 - s15. This patch enforces this limitation. Differential Revision: https://reviews.llvm.org/D59021 llvm-svn: 355707
2019-03-08 18:11:20 +01:00
VFMSL.F16 D0, S1, S16[0]
vfmal.f16 d0, s1, s16[0]
VFMSL.F16 Q0, D1, D8[0]
vfmal.f16 q0, d1, d8[0]
[ARM/AArch64] Support FP16 +fp16fml instructions Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
2018-08-17 13:29:49 +02:00
//CHECK-ERROR: error: invalid operand for instruction
//CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[2]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[-1]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[4]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D2[4]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1]
//CHECK-ERROR-NEXT: ^
[ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operand The indexed variant of vfmal.f16 and vfmsl.f16 instructions use the uppser bits of the indexed operand to store the index (1 bit for the double variant, 2 bits for the quad). This limits the usable registers to d0 - d7 or s0 - s15. This patch enforces this limitation. Differential Revision: https://reviews.llvm.org/D59021 llvm-svn: 355707
2019-03-08 18:11:20 +01:00
//CHECK-ERROR-NEXT: error: invalid instruction, any one of the following would fix this:
//CHECK-ERROR-NEXT: VFMSL.F16 D0, S1, S16[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: note: operand must be a register in range [s0, s15]
//CHECK-ERROR-NEXT: VFMSL.F16 D0, S1, S16[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: note: too many operands for instruction
//CHECK-ERROR-NEXT: VFMSL.F16 D0, S1, S16[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid instruction, any one of the following would fix this:
//CHECK-ERROR-NEXT: vfmal.f16 d0, s1, s16[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: note: operand must be a register in range [s0, s15]
//CHECK-ERROR-NEXT: vfmal.f16 d0, s1, s16[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: note: too many operands for instruction
//CHECK-ERROR-NEXT: vfmal.f16 d0, s1, s16[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this:
//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7]
//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: : note: too many operands for instruction
//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this:
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7]
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: 1: note: too many operands for instruction
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
//CHECK-ERROR-NEXT: ^
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