2012-12-11 22:25:42 +01:00
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//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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2018-05-01 17:54:18 +02:00
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/// Parent TargetRegisterInfo class common to all hw codegen targets.
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2012-12-11 22:25:42 +01:00
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 04:03:23 +02:00
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#include "SIMachineFunctionInfo.h"
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2017-05-17 23:56:25 +02:00
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#include "SIRegisterInfo.h"
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 04:03:23 +02:00
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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2012-12-11 22:25:42 +01:00
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using namespace llvm;
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2015-03-11 19:43:21 +01:00
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AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
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2012-12-11 22:25:42 +01:00
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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2018-05-04 00:38:06 +02:00
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
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2013-08-15 01:24:32 +02:00
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static const unsigned SubRegs[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
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AMDGPU::sub15
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};
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2014-05-15 23:44:05 +02:00
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assert(Channel < array_lengthof(SubRegs));
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2013-08-15 01:24:32 +02:00
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return SubRegs[Channel];
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}
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
Summary:
Move reserveRegisterTuples into AMDGPURegisterInfo and use it in
R600RegisterInfo::getReservedRegs and
R600InstrInfo::reserveIndirectRegisters to ensure that all super
registers of reserved registers are also marked as reserved.
Before this change, under certain circumstances, the registers %t1_x and
%t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not
be, leading to the register allocator sometimes assigning a register to
%t1_xy, which is invalid since %t1_x is reserved.
Reviewers: arsenm, tstellar, MatzeB, qcolombet
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D42448
llvm-svn: 323356
2018-01-24 19:09:53 +01:00
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void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
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MCRegAliasIterator R(Reg, this, true);
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for (; R.isValid(); ++R)
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Reserved.set(*R);
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}
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2012-12-11 22:25:42 +01:00
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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2017-05-17 23:56:25 +02:00
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// Forced to be here by one .inc
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const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
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const MachineFunction *MF) const {
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2017-12-15 23:22:58 +01:00
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CallingConv::ID CC = MF->getFunction().getCallingConv();
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2017-05-17 23:56:25 +02:00
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switch (CC) {
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case CallingConv::C:
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case CallingConv::Fast:
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2017-09-13 23:55:52 +02:00
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case CallingConv::Cold:
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2017-05-17 23:56:25 +02:00
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return CSR_AMDGPU_HighRegs_SaveList;
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default: {
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// Dummy to not crash RegisterClassInfo.
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static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
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return &NoCalleeSavedReg;
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}
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}
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}
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2017-08-01 21:54:18 +02:00
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const MCPhysReg *
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SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
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2017-09-14 19:14:57 +02:00
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return nullptr;
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2017-08-01 21:54:18 +02:00
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}
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2017-05-17 23:56:25 +02:00
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const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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switch (CC) {
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case CallingConv::C:
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case CallingConv::Fast:
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2017-09-13 23:55:52 +02:00
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case CallingConv::Cold:
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2017-05-17 23:56:25 +02:00
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return CSR_AMDGPU_HighRegs_RegMask;
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default:
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return nullptr;
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}
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}
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unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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2018-03-28 01:26:59 +02:00
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const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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return FuncInfo->getFrameOffsetReg();
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2017-05-17 23:56:25 +02:00
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}
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