2014-05-24 14:50:23 +02:00
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//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
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2014-03-29 11:18:08 +01:00
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2014-03-29 11:18:08 +01:00
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//
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//===----------------------------------------------------------------------===//
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//
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2014-05-24 14:50:23 +02:00
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// This class prints an AArch64 MCInst to a .s file.
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2014-03-29 11:18:08 +01:00
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
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#define LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
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2014-03-29 11:18:08 +01:00
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2014-05-24 14:50:23 +02:00
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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2017-02-03 22:49:13 +01:00
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#include "llvm/ADT/StringRef.h"
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2014-03-29 11:18:08 +01:00
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#include "llvm/MC/MCInstPrinter.h"
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2018-01-22 11:46:00 +01:00
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#include "../Utils/AArch64BaseInfo.h"
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2014-03-29 11:18:08 +01:00
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namespace llvm {
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2014-05-24 14:50:23 +02:00
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class AArch64InstPrinter : public MCInstPrinter {
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2014-03-29 11:18:08 +01:00
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public:
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2014-05-24 14:50:23 +02:00
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AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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2015-03-30 23:52:26 +02:00
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const MCRegisterInfo &MRI);
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
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const MCSubtargetInfo &STI) override;
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2014-04-29 09:58:25 +02:00
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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2014-03-29 11:18:08 +01:00
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// Autogenerated by tblgen.
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2015-03-27 21:36:02 +01:00
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virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O);
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virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O);
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2014-05-12 20:04:06 +02:00
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virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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2015-03-27 21:36:02 +01:00
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unsigned PrintMethodIdx,
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const MCSubtargetInfo &STI,
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raw_ostream &O);
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2017-02-03 22:49:13 +01:00
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2014-03-29 11:18:08 +01:00
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virtual StringRef getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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}
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2017-02-03 22:49:13 +01:00
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2014-03-29 11:18:08 +01:00
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static const char *getRegisterName(unsigned RegNo,
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2014-05-24 14:50:23 +02:00
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unsigned AltIdx = AArch64::NoRegAltName);
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2014-03-29 11:18:08 +01:00
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protected:
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2015-11-26 16:28:47 +01:00
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bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O);
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2014-03-29 11:18:08 +01:00
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// Operand printers
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2015-03-27 21:36:02 +01:00
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void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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2016-05-13 20:00:09 +02:00
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void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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2015-03-27 21:36:02 +01:00
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raw_ostream &O);
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2018-05-25 11:47:52 +02:00
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template <typename T> void printImmSVE(T Value, raw_ostream &O);
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2014-03-29 11:18:08 +01:00
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void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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raw_ostream &O);
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2015-03-27 21:36:02 +01:00
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template <int Amount>
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void printPostIncOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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2014-04-30 13:43:36 +02:00
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printPostIncOperand(MI, OpNo, Amount, O);
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}
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2015-03-27 21:36:02 +01:00
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void printVRegOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printSysCROperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printAddSubImm(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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[AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code
Summary:
All variants of isLogicalImm[Not](32|64) can be combined into a single templated function, same for printLogicalImm(32|64).
By making it use a template instead, further SVE patches can use it for other data types as well (e.g. 8, 16 bits).
Reviewers: fhahn, rengolin, aadg, echristo, kristof.beyls, samparker
Reviewed By: samparker
Subscribers: aemerson, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D42294
llvm-svn: 323646
2018-01-29 14:05:38 +01:00
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template <typename T>
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void printLogicalImm(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2015-03-27 21:36:02 +01:00
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void printShifter(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printShiftedRegister(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExtendedRegister(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printArithExtend(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-05-22 13:56:09 +02:00
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void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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char SrcRegKind, unsigned Width);
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template <char SrcRegKind, unsigned Width>
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2015-03-27 21:36:02 +01:00
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void printMemExtend(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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2014-05-22 13:56:09 +02:00
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printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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}
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[AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.
This patch adds parsing support for 'vector + shift/extend' and
corresponding asm operand classes, needed for implementing SVE's
gather/scatter addressing modes.
The added combinations of vector (ZPR) and Shift/Extend are:
Unscaled:
ZPR64ExtLSL8: signed 64-bit offsets (z0.d)
ZPR32ExtUXTW8: unsigned 32-bit offsets (z0.s, uxtw)
ZPR32ExtSXTW8: signed 32-bit offsets (z0.s, sxtw)
Unpacked and unscaled:
ZPR64ExtUXTW8: unsigned 32-bit offsets (z0.d, uxtw)
ZPR64ExtSXTW8: signed 32-bit offsets (z0.d, sxtw)
Unpacked and scaled:
ZPR64ExtUXTW<scale>: unsigned 32-bit offsets (z0.d, uxtw #<shift>)
ZPR64ExtSXTW<scale>: signed 32-bit offsets (z0.d, sxtw #<shift>)
Scaled:
ZPR32ExtUXTW<scale>: unsigned 32-bit offsets (z0.s, uxtw #<shift>)
ZPR32ExtSXTW<scale>: signed 32-bit offsets (z0.s, sxtw #<shift>)
ZPR64ExtLSL<scale>: unsigned 64-bit offsets (z0.d, lsl #<shift>)
ZPR64ExtLSL<scale>: signed 64-bit offsets (z0.d, lsl #<shift>)
Patch [1/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45951
llvm-svn: 330805
2018-04-25 11:26:47 +02:00
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template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix>
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2018-04-20 10:54:49 +02:00
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void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2015-03-27 21:36:02 +01:00
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void printCondCode(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printInverseCondCode(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printAlignedLabel(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-05-22 13:56:09 +02:00
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void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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2014-04-09 16:44:31 +02:00
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void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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template <int Scale>
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void printUImm12Offset(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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2014-05-22 13:56:09 +02:00
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printUImm12Offset(MI, OpNum, Scale, O);
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2014-04-09 16:44:31 +02:00
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}
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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template <int BitWidth>
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void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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2014-04-30 13:43:36 +02:00
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printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
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2014-04-09 16:44:31 +02:00
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}
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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void printAMNoIndex(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-04-30 13:43:36 +02:00
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2015-03-27 21:36:02 +01:00
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template <int Scale>
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void printImmScale(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-04-30 13:43:36 +02:00
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2018-05-14 13:54:41 +02:00
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template <bool IsSVEPrefetch = false>
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2015-03-27 21:36:02 +01:00
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void printPrefetchOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2015-12-01 11:48:51 +01:00
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void printPSBHintOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-04-30 13:43:36 +02:00
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2018-09-27 16:54:33 +02:00
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void printBTIHintOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2015-03-27 21:36:02 +01:00
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void printFPImmOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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void printVectorList(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O,
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2014-03-29 11:18:08 +01:00
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StringRef LayoutSuffix);
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/// Print a list of vector registers where the type suffix is implicit
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/// (i.e. attached to the instruction rather than the registers).
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void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
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2015-03-27 21:36:02 +01:00
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const MCSubtargetInfo &STI,
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2014-03-29 11:18:08 +01:00
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raw_ostream &O);
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template <unsigned NumLanes, char LaneKind>
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2015-03-27 21:36:02 +01:00
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void printTypedVectorList(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printVectorIndex(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printAdrpLabel(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printBarrierOption(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printSystemPStateField(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2017-08-31 11:27:04 +02:00
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template<int64_t Angle, int64_t Remainder>
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void printComplexRotationOp(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2015-06-02 12:58:41 +02:00
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template<unsigned size>
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void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O);
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2018-05-25 11:47:52 +02:00
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template <typename T>
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void printImm8OptLsl(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2018-06-01 09:25:46 +02:00
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template <typename T>
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void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2018-01-22 11:46:00 +01:00
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void printSVEPattern(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2017-11-07 17:45:48 +01:00
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template <char = 0>
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void printSVERegOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2018-07-02 09:34:52 +02:00
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void printGPR64as32(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2018-06-04 09:07:35 +02:00
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template <int Width>
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void printZPRasFPR(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2018-06-15 15:11:49 +02:00
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template <unsigned ImmIs0, unsigned ImmIs1>
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void printExactFPImm(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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2014-03-29 11:18:08 +01:00
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};
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2014-05-24 14:50:23 +02:00
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class AArch64AppleInstPrinter : public AArch64InstPrinter {
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2014-03-29 11:18:08 +01:00
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public:
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2014-05-24 14:50:23 +02:00
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AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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2015-03-30 23:52:26 +02:00
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const MCRegisterInfo &MRI);
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
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const MCSubtargetInfo &STI) override;
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2014-03-29 11:18:08 +01:00
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2015-03-27 21:36:02 +01:00
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void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O) override;
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bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O) override;
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2014-09-03 13:41:21 +02:00
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void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx,
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2015-03-27 21:36:02 +01:00
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const MCSubtargetInfo &STI,
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2014-09-03 13:41:21 +02:00
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raw_ostream &O) override;
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2017-02-03 22:49:13 +01:00
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2014-04-29 09:58:25 +02:00
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StringRef getRegName(unsigned RegNo) const override {
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2014-03-29 11:18:08 +01:00
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return getRegisterName(RegNo);
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}
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2017-02-03 22:49:13 +01:00
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2014-03-29 11:18:08 +01:00
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static const char *getRegisterName(unsigned RegNo,
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2014-05-24 14:50:23 +02:00
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unsigned AltIdx = AArch64::NoRegAltName);
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2014-03-29 11:18:08 +01:00
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};
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2017-02-03 22:49:13 +01:00
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
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