2012-12-11 22:25:42 +01:00
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//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2012-12-11 22:25:42 +01:00
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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2018-05-01 17:54:18 +02:00
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/// SI DAG Lowering interface definition
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2012-12-11 22:25:42 +01:00
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//
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//===----------------------------------------------------------------------===//
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2016-03-11 09:00:27 +01:00
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
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2012-12-11 22:25:42 +01:00
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#include "AMDGPUISelLowering.h"
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2017-08-04 01:00:29 +02:00
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#include "AMDGPUArgumentUsageInfo.h"
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2012-12-11 22:25:42 +01:00
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namespace llvm {
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2020-12-25 16:52:14 +01:00
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class GCNSubtarget;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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namespace AMDGPU {
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struct ImageDimIntrinsicInfo;
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}
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2016-03-11 09:00:27 +01:00
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class SITargetLowering final : public AMDGPUTargetLowering {
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AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 01:47:12 +02:00
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private:
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2018-07-11 22:59:01 +02:00
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const GCNSubtarget *Subtarget;
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AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 01:47:12 +02:00
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2018-07-28 16:11:34 +02:00
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public:
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MVT getRegisterTypeForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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unsigned getVectorTypeBreakdownForCallingConv(
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LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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unsigned &NumIntermediates, MVT &RegisterVT) const override;
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private:
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2017-04-12 00:29:24 +02:00
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SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Chain, uint64_t Offset) const;
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2017-07-28 17:52:08 +02:00
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SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
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2017-04-12 00:29:24 +02:00
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SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
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const SDLoc &SL, SDValue Chain,
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2020-06-29 13:56:06 +02:00
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uint64_t Offset, Align Alignment,
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bool Signed,
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2017-04-12 00:29:24 +02:00
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const ISD::InputArg *Arg = nullptr) const;
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2017-05-17 23:56:25 +02:00
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SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
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const SDLoc &SL, SDValue Chain,
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const ISD::InputArg &Arg) const;
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2017-08-04 01:00:29 +02:00
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SDValue getPreloadedValue(SelectionDAG &DAG,
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const SIMachineFunctionInfo &MFI,
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EVT VT,
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AMDGPUFunctionArgInfo::PreloadedValue) const;
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2017-05-17 23:56:25 +02:00
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2016-06-14 22:29:59 +02:00
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const override;
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2015-11-30 22:15:45 +01:00
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SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
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MVT VT, unsigned Offset) const;
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AMDGPU: Select MIMG instructions manually in SITargetLowering
Summary:
Having TableGen patterns for image intrinsics is hitting limitations:
for D16 we already have to manually pre-lower the packing of data
values, and we will have to do the same for A16 eventually.
Since there is already some custom C++ code anyway, it is arguably easier
to just do everything in C++, now that we can use the beefed-up generic
tables backend of TableGen to provide all the required metadata and map
intrinsics to corresponding opcodes. With this approach, all image
intrinsic lowering happens in SITargetLowering::lowerImage. That code is
dense due to all the cases that it handles, but it should still be easier
to follow than what we had before, by virtue of it all being done in a
single location, and by virtue of not relying on the TableGen pattern
magic that very few people really understand.
This means that we will have MachineSDNodes with MIMG instructions
during DAG combining, but that seems alright: previously we had
intrinsic nodes instead, but those are similarly opaque to the generic
CodeGen infrastructure, and the final pattern matching just did a 1:1
translation to machine instructions anyway. If anything, the fact that
we now merge the address words into a vector before DAG combine should
be an advantage.
Change-Id: I417f26bd88f54ce9781c1668acc01f3f99774de6
Reviewers: arsenm, rampitec, rtaylor, tstellar
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48017
llvm-svn: 335228
2018-06-21 15:36:57 +02:00
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SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
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2020-09-30 14:15:24 +02:00
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SelectionDAG &DAG, bool WithChain) const;
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AMDGPU: Divergence-driven selection of scalar buffer load intrinsics
Summary:
Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if
the load is really uniform. So select the scalar load intrinsics directly
to either VMEM or SMRD buffer loads based on divergence analysis.
If an offset happens to end up in a VGPR -- either because a floating
point calculation was involved, or due to other remaining deficiencies
in SIFixSGPRCopies -- we use v_readfirstlane.
There is some unrelated churn in tests since we now select MUBUF offsets
in a unified way with non-scalar buffer loads.
Change-Id: I170e6816323beb1348677b358c9d380865cd1a19
Reviewers: arsenm, alex-t, rampitec, tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53283
llvm-svn: 348050
2018-11-30 23:55:38 +01:00
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SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
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2020-01-30 03:03:07 +01:00
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SDValue CachePolicy, SelectionDAG &DAG) const;
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2015-11-30 22:15:45 +01:00
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2020-08-05 02:41:53 +02:00
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SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
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unsigned NewOpcode) const;
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SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
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unsigned NewOpcode) const;
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2014-07-26 08:23:37 +02:00
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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2016-04-12 16:05:04 +02:00
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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2014-07-26 08:23:37 +02:00
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 11:54:49 +02:00
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[AMDGPU] New tbuffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.tbuffer.load
llvm.amdgcn.struct.tbuffer.load
llvm.amdgcn.raw.tbuffer.store
llvm.amdgcn.struct.tbuffer.store
with the following changes from the llvm.amdgcn.tbuffer.* intrinsics:
* there are separate raw and struct versions: raw does not have an index
arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined format arg (dfmt+nfmt)
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::TBUFFER_* SD nodes always have an index operand, all three
offset operands, combined format operand, combined cachepolicy operand,
and an extra idxen operand.
The tbuffer pseudo- and real instructions now also have a combined
format operand.
The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store
intrinsics continue to work.
V2: Separate raw and struct intrinsics.
V3: Moved extract_glc and extract_slc defs to a more sensible place.
V4: Rebased on D49995.
V5: Only two separate offset args instead of three.
V6: Pseudo- and real instructions have joint format operand.
V7: Restored optionality of dfmt and nfmt in assembler.
V8: Addressed minor review comments.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D49026
Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4
llvm-svn: 340268
2018-08-21 13:06:05 +02:00
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// The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
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// (the offset that is included in bounds checking and swizzling, to be split
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// between the instruction's voffset and immoffset fields) and soffset (the
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// offset that is excluded from bounds checking and swizzling, to go in the
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// instruction's soffset field). This function takes the first kind of
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// offset and figures out how to split it between voffset and immoffset.
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std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
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SelectionDAG &DAG) const;
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AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 11:54:49 +02:00
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SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
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2013-11-14 00:36:50 +01:00
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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2014-02-04 18:18:40 +01:00
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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2016-07-20 01:16:53 +02:00
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SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
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2021-01-20 19:55:55 +01:00
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SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
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2016-07-20 01:16:53 +02:00
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SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
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2016-12-22 04:05:41 +01:00
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SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
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2014-07-15 22:18:31 +02:00
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SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
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2013-11-14 00:36:50 +01:00
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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2014-07-19 20:44:39 +02:00
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}
Summary:
Implement BUFFER_ATOMIC_CMPSWAP{,_X2} instructions on all GCN targets, and FLAT_ATOMIC_CMPSWAP{,_X2} on CI+.
32-bit instruction variants tested manually on Kabini and Bonaire. Tests and parts of code provided by Jan Veselý.
Patch by: Vedran Miletić
Reviewers: arsenm, tstellarAMD, nhaehnle
Subscribers: jvesely, scchan, kanarayan, arsenm
Differential Revision: http://reviews.llvm.org/D17280
llvm-svn: 265170
2016-04-01 20:27:37 +02:00
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SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
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2012-12-19 23:10:31 +01:00
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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2019-05-29 20:20:11 +02:00
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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2018-05-22 08:32:10 +02:00
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SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
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2018-08-03 01:33:01 +02:00
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SelectionDAG &DAG, ArrayRef<SDValue> Ops,
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2018-05-22 08:32:10 +02:00
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bool IsIntrinsic = false) const;
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2019-08-05 17:59:07 +02:00
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SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
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ArrayRef<SDValue> Ops) const;
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2019-03-22 15:58:02 +01:00
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// Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
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// dwordx4 if on SI.
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SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
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ArrayRef<SDValue> Ops, EVT MemVT,
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MachineMemOperand *MMO, SelectionDAG &DAG) const;
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[AMDGPU] Implement hardware bug workaround for image instructions
Summary:
This implements a workaround for a hardware bug in gfx8 and gfx9,
where register usage is not estimated correctly for image_store and
image_gather4 instructions when D16 is used.
Change-Id: I4e30744da6796acac53a9b5ad37ac1c2035c8899
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81172
2020-04-03 23:37:51 +02:00
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SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
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bool ImageStore = false) const;
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2018-01-12 22:12:19 +01:00
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2018-05-01 17:54:18 +02:00
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/// Converts \p Op, which must be of floating point type, to the
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2016-11-13 08:01:11 +01:00
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/// floating point type \p VT, by either extending or truncating it.
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2020-03-29 16:40:12 +02:00
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SDValue getFPExtOrFPRound(SelectionDAG &DAG,
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2016-11-13 08:01:11 +01:00
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SDValue Op,
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const SDLoc &DL,
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EVT VT) const;
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2017-04-12 00:29:24 +02:00
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SDValue convertArgType(
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SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
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bool Signed, const ISD::InputArg *Arg = nullptr) const;
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2018-05-01 17:54:18 +02:00
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/// Custom lowering for ISD::FP_ROUND for MVT::f16.
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2016-11-17 05:28:37 +01:00
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SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
|
2018-10-22 18:27:27 +02:00
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SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
|
2020-06-08 22:52:16 +02:00
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SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
|
2016-11-17 05:28:37 +01:00
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2017-04-07 01:02:33 +02:00
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SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
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SelectionDAG &DAG) const;
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2016-04-25 21:27:24 +02:00
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SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
|
2019-07-04 19:38:24 +02:00
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SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
2017-01-24 00:09:58 +01:00
|
|
|
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
2019-07-02 21:15:45 +02:00
|
|
|
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
2018-05-16 13:47:30 +02:00
|
|
|
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
2021-03-24 16:52:10 +01:00
|
|
|
|
2016-06-18 00:27:03 +02:00
|
|
|
SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
|
2021-03-24 16:52:10 +01:00
|
|
|
SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
|
2018-05-16 18:19:34 +02:00
|
|
|
SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
|
2016-04-25 21:27:24 +02:00
|
|
|
|
2017-12-04 23:18:27 +01:00
|
|
|
SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
|
2013-04-10 10:39:08 +02:00
|
|
|
|
2015-01-14 02:35:22 +01:00
|
|
|
SDValue performUCharToFloatCombine(SDNode *N,
|
|
|
|
|
DAGCombinerInfo &DCI) const;
|
2014-08-15 19:49:05 +02:00
|
|
|
SDValue performSHLPtrCombine(SDNode *N,
|
|
|
|
|
unsigned AS,
|
2017-11-13 06:11:54 +01:00
|
|
|
EVT MemVT,
|
2014-08-15 19:49:05 +02:00
|
|
|
DAGCombinerInfo &DCI) const;
|
2016-09-14 17:19:03 +02:00
|
|
|
|
2016-12-22 04:44:42 +01:00
|
|
|
SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
|
|
2016-09-14 17:19:03 +02:00
|
|
|
SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
|
|
|
|
|
unsigned Opc, SDValue LHS,
|
|
|
|
|
const ConstantSDNode *CRHS) const;
|
|
|
|
|
|
2015-01-07 00:00:46 +01:00
|
|
|
SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2015-01-07 00:00:39 +01:00
|
|
|
SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2016-09-14 17:19:03 +02:00
|
|
|
SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2017-03-31 21:53:03 +02:00
|
|
|
SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
Summary:
Add buffer store/load 8/16 overloaded intrinsics for buffer, raw_buffer and struct_buffer
Change-Id: I166a29f071b2ff4e4683fb0392564b1f223ac61d
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59265
llvm-svn: 356465
2019-03-19 17:07:00 +01:00
|
|
|
SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2015-01-07 00:00:39 +01:00
|
|
|
SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2018-08-07 00:10:26 +02:00
|
|
|
SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
|
|
|
|
|
const APFloat &C) const;
|
2016-04-14 03:42:16 +02:00
|
|
|
SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2014-06-11 19:50:44 +02:00
|
|
|
|
2017-02-22 00:35:48 +01:00
|
|
|
SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
|
|
|
|
|
SDValue Op0, SDValue Op1) const;
|
2017-02-27 23:40:39 +01:00
|
|
|
SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
|
|
|
|
|
SDValue Op0, SDValue Op1, bool Signed) const;
|
2016-01-28 21:53:42 +01:00
|
|
|
SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2017-02-22 00:35:48 +01:00
|
|
|
SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2017-02-22 01:27:34 +01:00
|
|
|
SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2017-05-11 19:26:25 +02:00
|
|
|
SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2018-11-19 18:39:20 +01:00
|
|
|
SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2016-01-28 21:53:42 +01:00
|
|
|
|
2019-02-14 23:11:25 +01:00
|
|
|
SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
|
2016-12-22 05:03:35 +01:00
|
|
|
unsigned getFusedOpcode(const SelectionDAG &DAG,
|
|
|
|
|
const SDNode *N0, const SDNode *N1) const;
|
2017-06-22 00:05:06 +02:00
|
|
|
SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2017-06-22 00:30:01 +02:00
|
|
|
SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
|
SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2016-12-22 04:44:42 +01:00
|
|
|
SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
|
SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2018-07-16 20:19:59 +02:00
|
|
|
SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2015-01-07 00:00:41 +01:00
|
|
|
SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2016-12-22 04:44:42 +01:00
|
|
|
SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2018-05-24 07:28:34 +02:00
|
|
|
SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2018-06-27 17:33:33 +02:00
|
|
|
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2014-11-14 21:08:52 +01:00
|
|
|
|
2015-07-20 16:28:41 +02:00
|
|
|
bool isLegalFlatAddressingMode(const AddrMode &AM) const;
|
2015-08-07 22:18:34 +02:00
|
|
|
bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
|
2016-02-13 00:45:29 +01:00
|
|
|
|
2017-03-17 21:41:45 +01:00
|
|
|
unsigned isCFIntrinsic(const SDNode *Intr) const;
|
2016-06-25 05:11:28 +02:00
|
|
|
|
2019-10-01 03:06:43 +02:00
|
|
|
public:
|
2016-10-20 20:12:38 +02:00
|
|
|
/// \returns True if fixup needs to be emitted for given global value \p GV,
|
|
|
|
|
/// false otherwise.
|
|
|
|
|
bool shouldEmitFixup(const GlobalValue *GV) const;
|
|
|
|
|
|
|
|
|
|
/// \returns True if GOT relocation needs to be emitted for given global value
|
|
|
|
|
/// \p GV, false otherwise.
|
|
|
|
|
bool shouldEmitGOTReloc(const GlobalValue *GV) const;
|
|
|
|
|
|
|
|
|
|
/// \returns True if PC-relative relocation needs to be emitted for given
|
|
|
|
|
/// global value \p GV, false otherwise.
|
|
|
|
|
bool shouldEmitPCReloc(const GlobalValue *GV) const;
|
|
|
|
|
|
2020-01-26 05:20:38 +01:00
|
|
|
/// \returns true if this should use a literal constant for an LDS address,
|
|
|
|
|
/// and not emit a relocation for an LDS global.
|
|
|
|
|
bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
|
|
|
|
|
|
2020-05-27 22:09:00 +02:00
|
|
|
/// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
|
|
|
|
|
/// expanded into a set of cmp/select instructions.
|
|
|
|
|
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
|
|
|
|
|
bool IsDivergentIdx);
|
|
|
|
|
|
2019-10-01 03:06:43 +02:00
|
|
|
private:
|
[AMDGPU] New buffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.buffer.load
llvm.amdgcn.raw.buffer.load.format
llvm.amdgcn.raw.buffer.load.format.d16
llvm.amdgcn.struct.buffer.load
llvm.amdgcn.struct.buffer.load.format
llvm.amdgcn.struct.buffer.load.format.d16
llvm.amdgcn.raw.buffer.store
llvm.amdgcn.raw.buffer.store.format
llvm.amdgcn.raw.buffer.store.format.d16
llvm.amdgcn.struct.buffer.store
llvm.amdgcn.struct.buffer.store.format
llvm.amdgcn.struct.buffer.store.format.d16
llvm.amdgcn.raw.buffer.atomic.*
llvm.amdgcn.struct.buffer.atomic.*
with the following changes from the llvm.amdgcn.buffer.*
intrinsics:
* there are separate raw and struct versions: raw does not have an
index arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::BUFFER_* SD nodes always have an index operand, all three
offset operands, combined cachepolicy operand, and an extra idxen
operand.
The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D50306
Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205
llvm-svn: 340269
2018-08-21 13:07:10 +02:00
|
|
|
// Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
|
|
|
|
|
// three offsets (voffset, soffset and instoffset) into the SDValue[3] array
|
|
|
|
|
// pointed to by Offsets.
|
AMDGPU: Add offsets to MMO when lowering buffer intrinsics
Summary:
Without offsets on the MachineMemOperands (MMOs),
MachineInstr::mayAlias() will return true for all reads and writes to the
same resource descriptor. This leads to O(N^2) complexity in the MachineScheduler
when analyzing dependencies of buffer loads and stores. It also limits
the SILoadStoreOptimizer from merging more instructions.
This patch reduces the compile time of one pathological compute shader
from 12 seconds to 1 second.
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65097
llvm-svn: 374087
2019-10-08 19:04:51 +02:00
|
|
|
/// \returns 0 If there is a non-constant offset or if the offset is 0.
|
|
|
|
|
/// Otherwise returns the constant offset.
|
|
|
|
|
unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
|
2020-06-29 13:56:06 +02:00
|
|
|
SDValue *Offsets, Align Alignment = Align(4)) const;
|
[AMDGPU] New buffer intrinsics
Summary:
This commit adds new intrinsics
llvm.amdgcn.raw.buffer.load
llvm.amdgcn.raw.buffer.load.format
llvm.amdgcn.raw.buffer.load.format.d16
llvm.amdgcn.struct.buffer.load
llvm.amdgcn.struct.buffer.load.format
llvm.amdgcn.struct.buffer.load.format.d16
llvm.amdgcn.raw.buffer.store
llvm.amdgcn.raw.buffer.store.format
llvm.amdgcn.raw.buffer.store.format.d16
llvm.amdgcn.struct.buffer.store
llvm.amdgcn.struct.buffer.store.format
llvm.amdgcn.struct.buffer.store.format.d16
llvm.amdgcn.raw.buffer.atomic.*
llvm.amdgcn.struct.buffer.atomic.*
with the following changes from the llvm.amdgcn.buffer.*
intrinsics:
* there are separate raw and struct versions: raw does not have an
index arg and sets idxen=0 in the instruction, and struct always sets
idxen=1 in the instruction even if the index is 0, to allow for the
fact that gfx9 does bounds checking differently depending on whether
idxen is set;
* there is a combined cachepolicy arg (glc+slc)
* there are now only two offset args: one for the offset that is
included in bounds checking and swizzling, to be split between the
instruction's voffset and immoffset fields, and one for the offset
that is excluded from bounds checking and swizzling, to go into the
instruction's soffset field.
The AMDISD::BUFFER_* SD nodes always have an index operand, all three
offset operands, combined cachepolicy operand, and an extra idxen
operand.
The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D50306
Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205
llvm-svn: 340269
2018-08-21 13:07:10 +02:00
|
|
|
|
[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
Summary:
Add buffer store/load 8/16 overloaded intrinsics for buffer, raw_buffer and struct_buffer
Change-Id: I166a29f071b2ff4e4683fb0392564b1f223ac61d
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59265
llvm-svn: 356465
2019-03-19 17:07:00 +01:00
|
|
|
// Handle 8 bit and 16 bit buffer loads
|
|
|
|
|
SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
|
|
|
|
|
ArrayRef<SDValue> Ops, MemSDNode *M) const;
|
|
|
|
|
|
|
|
|
|
// Handle 8 bit and 16 bit buffer stores
|
|
|
|
|
SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
|
|
|
|
|
SDLoc DL, SDValue Ops[],
|
|
|
|
|
MemSDNode *M) const;
|
|
|
|
|
|
2012-12-11 22:25:42 +01:00
|
|
|
public:
|
2018-07-11 22:59:01 +02:00
|
|
|
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
|
2016-06-24 08:30:11 +02:00
|
|
|
|
2018-07-11 22:59:01 +02:00
|
|
|
const GCNSubtarget *getSubtarget() const;
|
2014-08-15 19:17:07 +02:00
|
|
|
|
2019-10-29 00:06:34 +01:00
|
|
|
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
|
|
|
|
|
EVT SrcVT) const override;
|
2018-05-22 21:37:55 +02:00
|
|
|
|
2017-07-26 10:06:58 +02:00
|
|
|
bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
|
2017-03-16 00:15:12 +01:00
|
|
|
|
2016-04-12 16:05:04 +02:00
|
|
|
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
|
2017-12-14 23:34:10 +01:00
|
|
|
MachineFunction &MF,
|
2016-04-12 16:05:04 +02:00
|
|
|
unsigned IntrinsicID) const override;
|
|
|
|
|
|
2017-03-16 00:15:12 +01:00
|
|
|
bool getAddrModeArguments(IntrinsicInst * /*I*/,
|
|
|
|
|
SmallVectorImpl<Value*> &/*Ops*/,
|
|
|
|
|
Type *&/*AccessTy*/) const override;
|
2014-10-21 18:25:08 +02:00
|
|
|
|
[AMDGPU] Promote constant offset to the immediate by finding a new base with 13bit constant offset from the nearby instructions.
Summary: Promote constant offset to immediate by recomputing the relative 13bit offset from nearby instructions.
E.g.
s_movk_i32 s0, 0x1800
v_add_co_u32_e32 v0, vcc, s0, v2
v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
s_movk_i32 s0, 0x1000
v_add_co_u32_e32 v5, vcc, s0, v2
v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
global_load_dwordx2 v[5:6], v[5:6], off
global_load_dwordx2 v[0:1], v[0:1], off
=>
s_movk_i32 s0, 0x1000
v_add_co_u32_e32 v5, vcc, s0, v2
v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
global_load_dwordx2 v[5:6], v[5:6], off
global_load_dwordx2 v[0:1], v[5:6], off offset:2048
Author: FarhanaAleen
Reviewed By: arsenm, rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D55539
llvm-svn: 349196
2018-12-14 22:13:14 +01:00
|
|
|
bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
|
2015-07-09 04:09:40 +02:00
|
|
|
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
|
2017-07-21 13:59:37 +02:00
|
|
|
unsigned AS,
|
|
|
|
|
Instruction *I = nullptr) const override;
|
2014-08-15 19:17:07 +02:00
|
|
|
|
2017-07-10 22:25:54 +02:00
|
|
|
bool canMergeStoresTo(unsigned AS, EVT MemVT,
|
|
|
|
|
const SelectionDAG &DAG) const override;
|
2017-05-24 17:59:09 +02:00
|
|
|
|
2019-09-10 18:20:14 +02:00
|
|
|
bool allowsMisalignedMemoryAccessesImpl(
|
2020-07-31 17:04:13 +02:00
|
|
|
unsigned Size, unsigned AddrSpace, Align Alignment,
|
2019-09-10 18:20:14 +02:00
|
|
|
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
|
|
|
|
|
bool *IsFast = nullptr) const;
|
|
|
|
|
|
2019-06-12 19:14:03 +02:00
|
|
|
bool allowsMisalignedMemoryAccesses(
|
2020-07-31 17:04:13 +02:00
|
|
|
LLT Ty, unsigned AddrSpace, Align Alignment,
|
|
|
|
|
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
|
|
|
|
|
bool *IsFast = nullptr) const override {
|
|
|
|
|
if (IsFast)
|
|
|
|
|
*IsFast = false;
|
|
|
|
|
return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
|
|
|
|
|
Alignment, Flags, IsFast);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool allowsMisalignedMemoryAccesses(
|
2021-02-05 04:22:04 +01:00
|
|
|
EVT VT, unsigned AS, Align Alignment,
|
2019-06-12 19:14:03 +02:00
|
|
|
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
|
|
|
|
|
bool *IsFast = nullptr) const override;
|
2014-07-03 02:23:43 +02:00
|
|
|
|
[NFC] Introduce a type to model memory operation
Summary: This is a first step before changing the types to llvm::Align and introduce functions to ease client code.
Reviewers: courbet
Subscribers: arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, jsji, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73785
2020-01-31 15:40:31 +01:00
|
|
|
EVT getOptimalMemOpType(const MemOp &Op,
|
2019-04-30 10:38:12 +02:00
|
|
|
const AttributeList &FuncAttributes) const override;
|
2014-07-28 19:49:26 +02:00
|
|
|
|
2015-12-15 21:55:55 +01:00
|
|
|
bool isMemOpUniform(const SDNode *N) const;
|
2016-12-08 18:28:47 +01:00
|
|
|
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
|
2019-10-08 19:04:41 +02:00
|
|
|
|
2020-12-25 16:52:14 +01:00
|
|
|
static bool isNonGlobalAddrSpace(unsigned AS);
|
2020-02-16 04:34:37 +01:00
|
|
|
|
2019-06-03 20:41:34 +02:00
|
|
|
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
|
2015-12-02 00:04:00 +01:00
|
|
|
|
2014-07-03 02:23:43 +02:00
|
|
|
TargetLoweringBase::LegalizeTypeAction
|
2018-11-06 00:26:13 +01:00
|
|
|
getPreferredVectorAction(MVT VT) const override;
|
2013-03-07 10:03:52 +01:00
|
|
|
|
2014-04-29 09:57:24 +02:00
|
|
|
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
|
|
|
|
Type *Ty) const override;
|
2014-03-31 21:54:27 +02:00
|
|
|
|
2016-01-20 01:13:22 +01:00
|
|
|
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
|
|
|
|
|
|
2016-06-25 03:59:16 +02:00
|
|
|
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
|
|
|
|
|
|
2017-08-01 21:54:18 +02:00
|
|
|
bool supportSplitCSR(MachineFunction *MF) const override;
|
|
|
|
|
void initializeSplitCSR(MachineBasicBlock *Entry) const override;
|
|
|
|
|
void insertCopiesSplitCSR(
|
|
|
|
|
MachineBasicBlock *Entry,
|
|
|
|
|
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
|
|
|
|
|
|
2013-03-07 10:03:52 +01:00
|
|
|
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
|
|
|
|
|
bool isVarArg,
|
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2016-06-12 17:39:02 +02:00
|
|
|
const SDLoc &DL, SelectionDAG &DAG,
|
2014-04-29 09:57:24 +02:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
2013-03-07 10:03:52 +01:00
|
|
|
|
2017-05-17 23:56:25 +02:00
|
|
|
bool CanLowerReturn(CallingConv::ID CallConv,
|
|
|
|
|
MachineFunction &MF, bool isVarArg,
|
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
|
LLVMContext &Context) const override;
|
|
|
|
|
|
|
|
|
|
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
|
2016-01-13 18:23:04 +01:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2016-06-12 17:39:02 +02:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
|
|
|
|
|
SelectionDAG &DAG) const override;
|
2016-01-13 18:23:04 +01:00
|
|
|
|
2017-08-04 01:00:29 +02:00
|
|
|
void passSpecialInputs(
|
|
|
|
|
CallLoweringInfo &CLI,
|
2018-08-22 13:09:45 +02:00
|
|
|
CCState &CCInfo,
|
2017-08-04 01:00:29 +02:00
|
|
|
const SIMachineFunctionInfo &Info,
|
|
|
|
|
SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
|
|
|
|
|
SmallVectorImpl<SDValue> &MemOpChains,
|
2018-08-22 13:09:45 +02:00
|
|
|
SDValue Chain) const;
|
2017-08-04 01:00:29 +02:00
|
|
|
|
2017-08-01 21:54:18 +02:00
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
|
const SDLoc &DL, SelectionDAG &DAG,
|
|
|
|
|
SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
|
|
|
|
|
SDValue ThisVal) const;
|
2017-08-11 22:42:08 +02:00
|
|
|
|
|
|
|
|
bool mayBeEmittedAsTailCall(const CallInst *) const override;
|
|
|
|
|
|
|
|
|
|
bool isEligibleForTailCallOptimization(
|
|
|
|
|
SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
|
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
|
|
|
|
|
|
2017-08-01 21:54:18 +02:00
|
|
|
SDValue LowerCall(CallLoweringInfo &CLI,
|
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
|
|
2020-05-27 16:59:14 +02:00
|
|
|
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
|
2019-12-28 15:18:56 +01:00
|
|
|
Register getRegisterByName(const char* RegName, LLT VT,
|
2019-10-01 03:44:39 +02:00
|
|
|
const MachineFunction &MF) const override;
|
2016-01-26 05:29:24 +01:00
|
|
|
|
2016-07-12 23:41:32 +02:00
|
|
|
MachineBasicBlock *splitKillBlock(MachineInstr &MI,
|
|
|
|
|
MachineBasicBlock *BB) const;
|
|
|
|
|
|
2019-07-19 21:47:30 +02:00
|
|
|
void bundleInstWithWaitcnt(MachineInstr &MI) const;
|
2019-06-20 22:54:32 +02:00
|
|
|
MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
|
|
|
|
|
MachineBasicBlock *BB) const;
|
|
|
|
|
|
2016-07-01 00:52:52 +02:00
|
|
|
MachineBasicBlock *
|
|
|
|
|
EmitInstrWithCustomInserter(MachineInstr &MI,
|
|
|
|
|
MachineBasicBlock *BB) const override;
|
2017-10-13 23:10:22 +02:00
|
|
|
|
|
|
|
|
bool hasBitPreservingFPLogic(EVT VT) const override;
|
2015-01-29 20:34:32 +01:00
|
|
|
bool enableAggressiveFMAFusion(EVT VT) const override;
|
2015-07-09 04:09:04 +02:00
|
|
|
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
|
|
|
|
|
EVT VT) const override;
|
2015-07-09 17:12:23 +02:00
|
|
|
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
|
2020-08-15 19:38:29 +02:00
|
|
|
LLT getPreferredShiftAmountTy(LLT Ty) const override;
|
|
|
|
|
|
2019-10-29 01:38:44 +01:00
|
|
|
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
|
|
|
|
|
EVT VT) const override;
|
2020-04-12 15:47:03 +02:00
|
|
|
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
|
2019-10-28 19:00:12 +01:00
|
|
|
|
2018-06-15 17:15:46 +02:00
|
|
|
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
|
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
|
[AMDGPU] Enable v4f16 and above for v_pk_fma instructions
Summary:
If isel is presented with <2 x half> vectors then it will correctly select
v_pk_fma style instructions.
If isel is presented with e.g. <4 x half> vectors it will scalarize, unlike for
other instruction types (such as fadd, fmul etc.)
Added extra support to enable this. Updated one of the tests to include a test
for this (as well as extending the test to GFX9)
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65325
Change-Id: I50a4577a3f8223fb53992af3b7d26121f65b71ee
llvm-svn: 367206
2019-07-29 10:15:10 +02:00
|
|
|
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
|
2014-04-29 09:57:24 +02:00
|
|
|
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
2018-06-15 17:15:46 +02:00
|
|
|
|
2017-01-24 00:09:58 +01:00
|
|
|
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
|
|
|
|
SelectionDAG &DAG) const override;
|
|
|
|
|
|
2014-04-29 09:57:24 +02:00
|
|
|
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
|
|
|
|
SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
|
2021-04-01 18:13:12 +02:00
|
|
|
void AddIMGInit(MachineInstr &MI) const;
|
2016-07-01 00:52:52 +02:00
|
|
|
void AdjustInstrPostInstrSelection(MachineInstr &MI,
|
2014-04-29 09:57:24 +02:00
|
|
|
SDNode *Node) const override;
|
2013-02-26 18:52:23 +01:00
|
|
|
|
2017-04-12 23:58:23 +02:00
|
|
|
SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
|
2014-11-05 20:01:17 +01:00
|
|
|
|
2016-06-12 17:39:02 +02:00
|
|
|
MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
|
|
|
|
|
SDValue Ptr) const;
|
|
|
|
|
MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
|
|
|
|
|
uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
|
2015-07-05 21:29:18 +02:00
|
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
|
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|
|
|
|
StringRef Constraint, MVT VT) const override;
|
2015-12-10 03:12:53 +01:00
|
|
|
ConstraintType getConstraintType(StringRef Constraint) const override;
|
2020-05-25 13:19:22 +02:00
|
|
|
void LowerAsmOperandForConstraint(SDValue Op,
|
|
|
|
|
std::string &Constraint,
|
|
|
|
|
std::vector<SDValue> &Ops,
|
|
|
|
|
SelectionDAG &DAG) const override;
|
2020-07-02 16:16:11 +02:00
|
|
|
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
|
|
|
|
|
bool checkAsmConstraintVal(SDValue Op,
|
|
|
|
|
const std::string &Constraint,
|
|
|
|
|
uint64_t Val) const;
|
|
|
|
|
bool checkAsmConstraintValA(SDValue Op,
|
|
|
|
|
uint64_t Val,
|
|
|
|
|
unsigned MaxSize = 64) const;
|
2016-06-12 17:39:02 +02:00
|
|
|
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
|
|
|
|
|
SDValue V) const;
|
2017-07-18 18:44:56 +02:00
|
|
|
|
|
|
|
|
void finalizeLowering(MachineFunction &MF) const override;
|
2017-11-15 01:45:43 +01:00
|
|
|
|
2020-06-04 16:27:45 +02:00
|
|
|
void computeKnownBitsForFrameIndex(int FrameIdx,
|
2017-11-15 01:45:43 +01:00
|
|
|
KnownBits &Known,
|
2020-06-04 16:27:45 +02:00
|
|
|
const MachineFunction &MF) const override;
|
2020-08-16 19:42:55 +02:00
|
|
|
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R,
|
|
|
|
|
KnownBits &Known,
|
|
|
|
|
const APInt &DemandedElts,
|
|
|
|
|
const MachineRegisterInfo &MRI,
|
|
|
|
|
unsigned Depth = 0) const override;
|
AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLowering
Summary:
The code that handles ISD:Register and ISD::CopyFromReg assumes
the target is amdgcn, so this is broken on r600. We don't
need this analysis on r600 anyway so we can safely move
it to SITargetLowering.
Reviewers: alex-t, arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: msearles, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46298
llvm-svn: 334607
2018-06-13 17:06:37 +02:00
|
|
|
|
2020-06-05 21:29:18 +02:00
|
|
|
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
|
|
|
|
|
const MachineRegisterInfo &MRI,
|
|
|
|
|
unsigned Depth = 0) const override;
|
AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLowering
Summary:
The code that handles ISD:Register and ISD::CopyFromReg assumes
the target is amdgcn, so this is broken on r600. We don't
need this analysis on r600 anyway so we can safely move
it to SITargetLowering.
Reviewers: alex-t, arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: msearles, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46298
llvm-svn: 334607
2018-06-13 17:06:37 +02:00
|
|
|
bool isSDNodeSourceOfDivergence(const SDNode *N,
|
2018-08-30 16:21:36 +02:00
|
|
|
FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
|
2018-08-06 23:38:27 +02:00
|
|
|
|
|
|
|
|
bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
|
|
|
|
|
unsigned MaxDepth = 5) const;
|
2021-04-27 12:21:57 +02:00
|
|
|
bool isCanonicalized(Register Reg, MachineFunction &MF,
|
|
|
|
|
unsigned MaxDepth = 5) const;
|
2019-11-01 02:50:30 +01:00
|
|
|
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
|
2021-04-27 12:21:57 +02:00
|
|
|
bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
|
2018-10-22 18:27:27 +02:00
|
|
|
|
|
|
|
|
bool isKnownNeverNaNForTargetNode(SDValue Op,
|
|
|
|
|
const SelectionDAG &DAG,
|
|
|
|
|
bool SNaN = false,
|
|
|
|
|
unsigned Depth = 0) const override;
|
2019-01-22 19:36:06 +01:00
|
|
|
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
|
2019-06-06 23:13:02 +02:00
|
|
|
|
2019-10-14 14:01:10 +02:00
|
|
|
virtual const TargetRegisterClass *
|
|
|
|
|
getRegClassFor(MVT VT, bool isDivergent) const override;
|
2020-05-26 18:58:18 +02:00
|
|
|
virtual bool requiresUniformRegister(MachineFunction &MF,
|
|
|
|
|
const Value *V) const override;
|
2019-09-27 14:54:21 +02:00
|
|
|
Align getPrefLoopAlignment(MachineLoop *ML) const override;
|
2019-07-19 16:15:18 +02:00
|
|
|
|
|
|
|
|
void allocateHSAUserSGPRs(CCState &CCInfo,
|
|
|
|
|
MachineFunction &MF,
|
|
|
|
|
const SIRegisterInfo &TRI,
|
|
|
|
|
SIMachineFunctionInfo &Info) const;
|
|
|
|
|
|
|
|
|
|
void allocateSystemSGPRs(CCState &CCInfo,
|
|
|
|
|
MachineFunction &MF,
|
|
|
|
|
SIMachineFunctionInfo &Info,
|
|
|
|
|
CallingConv::ID CallConv,
|
|
|
|
|
bool IsShader) const;
|
|
|
|
|
|
|
|
|
|
void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
|
|
|
|
|
MachineFunction &MF,
|
|
|
|
|
const SIRegisterInfo &TRI,
|
|
|
|
|
SIMachineFunctionInfo &Info) const;
|
|
|
|
|
void allocateSpecialInputSGPRs(
|
|
|
|
|
CCState &CCInfo,
|
|
|
|
|
MachineFunction &MF,
|
|
|
|
|
const SIRegisterInfo &TRI,
|
|
|
|
|
SIMachineFunctionInfo &Info) const;
|
|
|
|
|
|
|
|
|
|
void allocateSpecialInputVGPRs(CCState &CCInfo,
|
|
|
|
|
MachineFunction &MF,
|
|
|
|
|
const SIRegisterInfo &TRI,
|
|
|
|
|
SIMachineFunctionInfo &Info) const;
|
2020-03-11 21:13:52 +01:00
|
|
|
void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
|
|
|
|
|
MachineFunction &MF,
|
|
|
|
|
const SIRegisterInfo &TRI,
|
|
|
|
|
SIMachineFunctionInfo &Info) const;
|
2020-07-02 21:02:39 +02:00
|
|
|
|
2021-04-29 15:02:51 +02:00
|
|
|
std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL,
|
|
|
|
|
Type *Ty) const;
|
2012-12-11 22:25:42 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
} // End namespace llvm
|
|
|
|
|
|
2014-08-13 18:26:38 +02:00
|
|
|
#endif
|
