2015-10-12 18:07:25 +02:00
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//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class MMDSPInst<string opstr = "">
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: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
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let InsnPredicates = [HasDSP];
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2015-10-15 10:59:45 +02:00
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let AdditionalPredicates = [InMicroMips];
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2015-10-12 18:07:25 +02:00
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string BaseOpcode = opstr;
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string Arch = "mmdsp";
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let DecoderNamespace = "MicroMips";
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}
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2015-10-15 10:59:45 +02:00
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class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
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2015-10-12 18:07:25 +02:00
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10-0} = op;
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}
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2015-10-15 10:59:45 +02:00
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2015-10-19 08:34:44 +02:00
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class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-6} = op;
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<2> ac;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-14} = ac;
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let Inst{13-6} = op;
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let Inst{5-0} = 0b111100;
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}
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2015-10-19 09:16:26 +02:00
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class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0b0;
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let Inst{9-0} = op;
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}
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2015-10-23 08:39:29 +02:00
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class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<4> sa;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-12} = sa;
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let Inst{11-0} = op;
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}
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class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<3> sa;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-13} = sa;
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let Inst{12-6} = op;
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<5> sa;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = sa;
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let Inst{10} = 0b0;
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let Inst{9-0} = op;
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}
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2015-11-13 14:14:25 +01:00
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class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<4> sa;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-12} = sa;
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let Inst{11} = 0b0;
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let Inst{10-0} = op;
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}
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class POOL32A_2RSA4OP6_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<4> sa;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-12} = sa;
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let Inst{11-6} = op;
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let Inst{5-0} = 0b111100;
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}
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2015-11-17 13:54:15 +01:00
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class POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
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bits<5> rt;
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bits<5> imm;
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bits<2> ac;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = imm;
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let Inst{15-14} = ac;
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let Inst{13-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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