2007-10-12 23:30:57 +02:00
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//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
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2003-10-21 17:17:13 +02:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2003-10-21 17:17:13 +02:00
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//
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//===----------------------------------------------------------------------===//
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2003-08-03 17:47:25 +02:00
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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2003-08-04 06:59:56 +02:00
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let Namespace = "X86" in {
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2004-09-14 06:17:02 +02:00
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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2007-11-11 20:50:10 +01:00
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// Dwarf numbering is different for 32-bit and 64-bit, and there are
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// variations by target as well. Currently the first entry is for X86-64,
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2008-01-25 01:34:13 +01:00
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// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
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// and debug information on X86-32/Darwin)
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2007-11-07 22:48:35 +01:00
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2007-04-20 23:15:21 +02:00
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// 8-bit registers
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// Low registers
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2008-07-08 00:21:06 +02:00
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def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
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def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
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def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
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def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
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2006-09-08 08:48:29 +02:00
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// X86-64 only
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2008-07-08 00:21:06 +02:00
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def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
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def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
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def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
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def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
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def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
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def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
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def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
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def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
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def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
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def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
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def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
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def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
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2007-04-20 23:15:21 +02:00
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Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
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// High registers. On x86-64, these cannot be used in any instruction
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// with a REX prefix.
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2008-07-08 00:21:06 +02:00
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def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
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def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
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def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
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def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
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2006-09-08 08:48:29 +02:00
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2003-08-03 17:47:25 +02:00
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// 16-bit registers
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2009-04-13 17:18:42 +02:00
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def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
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def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
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def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
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def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
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2008-07-08 00:21:06 +02:00
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def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
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def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
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def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
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def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
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def IP : Register<"ip">, DwarfRegNum<[16]>;
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2003-08-03 17:47:25 +02:00
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2006-09-08 08:48:29 +02:00
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// X86-64 only
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2008-07-08 00:21:06 +02:00
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def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
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def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
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def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
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def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
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def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
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def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
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def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
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def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
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2006-09-08 08:48:29 +02:00
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2007-04-20 23:15:21 +02:00
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// 32-bit registers
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2008-07-08 00:21:06 +02:00
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def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
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def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
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def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
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def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
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def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
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def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
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def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
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def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
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def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
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2007-04-20 23:15:21 +02:00
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2006-09-08 08:48:29 +02:00
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// X86-64 only
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2008-07-08 00:21:06 +02:00
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def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
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def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
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def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
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def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
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def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
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def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
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def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
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def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
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2006-09-08 08:48:29 +02:00
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2007-04-20 23:15:21 +02:00
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// 64-bit registers, X86-64 only
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2008-07-08 00:21:06 +02:00
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def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
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def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
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def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
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def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
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def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
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def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
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def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
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def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
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def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
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def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
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def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
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def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
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def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
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def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
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def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
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def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
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def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
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2006-02-20 23:34:53 +01:00
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// MMX Registers. These are actually aliased to ST0 .. ST7
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2008-07-08 00:21:06 +02:00
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def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
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def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
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def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
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def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
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def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
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def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
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def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
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def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
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2003-08-03 17:47:25 +02:00
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// Pseudo Floating Point registers
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2008-07-08 00:21:06 +02:00
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def FP0 : Register<"fp0">;
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def FP1 : Register<"fp1">;
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def FP2 : Register<"fp2">;
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def FP3 : Register<"fp3">;
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def FP4 : Register<"fp4">;
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def FP5 : Register<"fp5">;
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def FP6 : Register<"fp6">;
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2003-08-03 17:47:25 +02:00
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2005-06-27 23:20:31 +02:00
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// XMM Registers, used by the various SSE instruction set extensions
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2008-07-08 00:21:06 +02:00
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def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
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def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
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def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
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def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
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def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
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def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
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def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
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def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
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2006-09-08 08:48:29 +02:00
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// X86-64 only
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2008-07-08 00:21:06 +02:00
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def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
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def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
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def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
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def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
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def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
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def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
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def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
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def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
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2005-06-27 23:20:31 +02:00
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2009-06-30 00:50:51 +02:00
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// YMM Registers, used by AVX instructions
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def YMM0: Register<"ymm0">, DwarfRegNum<[17, 21, 21]>;
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def YMM1: Register<"ymm1">, DwarfRegNum<[18, 22, 22]>;
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def YMM2: Register<"ymm2">, DwarfRegNum<[19, 23, 23]>;
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def YMM3: Register<"ymm3">, DwarfRegNum<[20, 24, 24]>;
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def YMM4: Register<"ymm4">, DwarfRegNum<[21, 25, 25]>;
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def YMM5: Register<"ymm5">, DwarfRegNum<[22, 26, 26]>;
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def YMM6: Register<"ymm6">, DwarfRegNum<[23, 27, 27]>;
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def YMM7: Register<"ymm7">, DwarfRegNum<[24, 28, 28]>;
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def YMM8: Register<"ymm8">, DwarfRegNum<[25, -2, -2]>;
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def YMM9: Register<"ymm9">, DwarfRegNum<[26, -2, -2]>;
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def YMM10: Register<"ymm10">, DwarfRegNum<[27, -2, -2]>;
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def YMM11: Register<"ymm11">, DwarfRegNum<[28, -2, -2]>;
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def YMM12: Register<"ymm12">, DwarfRegNum<[29, -2, -2]>;
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def YMM13: Register<"ymm13">, DwarfRegNum<[30, -2, -2]>;
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def YMM14: Register<"ymm14">, DwarfRegNum<[31, -2, -2]>;
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def YMM15: Register<"ymm15">, DwarfRegNum<[32, -2, -2]>;
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2003-08-03 17:47:25 +02:00
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// Floating point stack registers
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2008-07-08 00:21:06 +02:00
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def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
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def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
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def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
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def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
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def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
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def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
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def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
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def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
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2007-09-11 21:53:28 +02:00
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// Status flags register
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2009-03-04 02:41:49 +01:00
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def EFLAGS : Register<"flags">;
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2009-04-08 23:14:34 +02:00
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// Segment registers
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def CS : Register<"cs">;
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def DS : Register<"ds">;
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def SS : Register<"ss">;
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def ES : Register<"es">;
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def FS : Register<"fs">;
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def GS : Register<"gs">;
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2003-08-03 17:47:25 +02:00
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}
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2007-07-28 21:03:30 +02:00
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//===----------------------------------------------------------------------===//
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// Subregister Set Definitions... now that we have all of the pieces, define the
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// sub registers for each register.
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//
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2008-03-11 11:09:17 +01:00
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def x86_subreg_8bit : PatLeaf<(i32 1)>;
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Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
def x86_subreg_8bit_hi : PatLeaf<(i32 2)>;
|
|
|
|
def x86_subreg_16bit : PatLeaf<(i32 3)>;
|
|
|
|
def x86_subreg_32bit : PatLeaf<(i32 4)>;
|
2008-03-11 11:09:17 +01:00
|
|
|
|
2007-07-28 21:03:30 +02:00
|
|
|
def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
|
|
|
|
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
|
|
|
|
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
|
|
|
|
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
|
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
def : SubRegSet<2, [AX, CX, DX, BX],
|
|
|
|
[AH, CH, DH, BH]>;
|
2007-07-28 21:03:30 +02:00
|
|
|
|
|
|
|
def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
|
|
|
|
R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
|
|
|
|
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
|
|
|
|
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
|
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
def : SubRegSet<2, [EAX, ECX, EDX, EBX],
|
|
|
|
[AH, CH, DH, BH]>;
|
|
|
|
|
|
|
|
def : SubRegSet<3, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
|
2007-07-28 21:03:30 +02:00
|
|
|
R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
|
|
|
|
[AX, CX, DX, BX, SP, BP, SI, DI,
|
|
|
|
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
|
|
|
|
|
|
|
|
def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
|
|
|
|
R8, R9, R10, R11, R12, R13, R14, R15],
|
|
|
|
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
|
|
|
|
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
|
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
def : SubRegSet<2, [RAX, RCX, RDX, RBX],
|
|
|
|
[AH, CH, DH, BH]>;
|
|
|
|
|
|
|
|
def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
|
2007-07-28 21:03:30 +02:00
|
|
|
R8, R9, R10, R11, R12, R13, R14, R15],
|
|
|
|
[AX, CX, DX, BX, SP, BP, SI, DI,
|
|
|
|
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
|
|
|
|
def : SubRegSet<4, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
|
2007-07-28 21:03:30 +02:00
|
|
|
R8, R9, R10, R11, R12, R13, R14, R15],
|
|
|
|
[EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
|
|
|
|
R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
|
|
|
|
|
2009-06-30 00:50:51 +02:00
|
|
|
def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
|
|
|
|
YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
|
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
|
|
|
|
|
2003-08-03 17:47:25 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register Class Definitions... now that we have all of the pieces, define the
|
|
|
|
// top-level register classes. The order specified in the register list is
|
|
|
|
// implicitly defined to be the register allocation order.
|
|
|
|
//
|
2005-01-05 17:09:16 +01:00
|
|
|
|
2006-09-08 08:48:29 +02:00
|
|
|
// List call-clobbered registers before callee-save registers. RBX, RBP, (and
|
|
|
|
// R12, R13, R14, and R15 for X86-64) are callee-save registers.
|
|
|
|
// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
|
|
|
|
// R8B, ... R15B.
|
2008-11-19 18:19:35 +01:00
|
|
|
// Allocate R12 and R13 last, as these require an extra byte when
|
|
|
|
// encoded in x86_64 instructions.
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
|
|
|
|
// 64-bit mode. The main complication is that they cannot be encoded in an
|
|
|
|
// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
|
|
|
|
// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
|
|
|
|
// cannot be encoded.
|
2006-09-08 08:48:29 +02:00
|
|
|
def GR8 : RegisterClass<"X86", [i8], 8,
|
|
|
|
[AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
|
2008-11-19 18:19:35 +01:00
|
|
|
R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
|
2006-09-08 08:48:29 +02:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2009-01-27 20:25:38 +01:00
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate SPL or BPL.
|
|
|
|
static const unsigned X86_GR8_AO_64_fp[] = {
|
|
|
|
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
|
|
|
|
X86::R8B, X86::R9B, X86::R10B, X86::R11B,
|
|
|
|
X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B
|
|
|
|
};
|
|
|
|
// If not, just don't allocate SPL.
|
|
|
|
static const unsigned X86_GR8_AO_64[] = {
|
|
|
|
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
|
|
|
|
X86::R8B, X86::R9B, X86::R10B, X86::R11B,
|
|
|
|
X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
|
|
|
|
};
|
|
|
|
// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
|
|
|
|
static const unsigned X86_GR8_AO_32[] = {
|
|
|
|
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH
|
|
|
|
};
|
2006-09-08 08:48:29 +02:00
|
|
|
|
|
|
|
GR8Class::iterator
|
|
|
|
GR8Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 08:48:29 +02:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return X86_GR8_AO_32;
|
2007-01-23 01:57:47 +01:00
|
|
|
else if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR8_AO_64_fp;
|
|
|
|
else
|
|
|
|
return X86_GR8_AO_64;
|
|
|
|
}
|
2005-01-05 17:09:16 +01:00
|
|
|
|
2006-09-08 08:48:29 +02:00
|
|
|
GR8Class::iterator
|
|
|
|
GR8Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 08:48:29 +02:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
|
2007-01-23 01:57:47 +01:00
|
|
|
else if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
def GR16 : RegisterClass<"X86", [i16], 16,
|
|
|
|
[AX, CX, DX, SI, DI, BX, BP, SP,
|
2008-11-19 18:19:35 +01:00
|
|
|
R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
let SubRegClassList = [GR8, GR8];
|
2005-08-19 21:13:20 +02:00
|
|
|
let MethodProtos = [{
|
2006-09-08 08:48:29 +02:00
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
2006-08-18 00:00:08 +02:00
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
2005-08-19 21:13:20 +02:00
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2009-01-27 20:25:38 +01:00
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate SP or BP.
|
|
|
|
static const unsigned X86_GR16_AO_64_fp[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
|
|
|
|
X86::R8W, X86::R9W, X86::R10W, X86::R11W,
|
|
|
|
X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W
|
|
|
|
};
|
|
|
|
static const unsigned X86_GR16_AO_32_fp[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
|
|
|
|
};
|
2009-04-13 17:28:29 +02:00
|
|
|
// If not, just don't allocate SP.
|
2009-01-27 20:25:38 +01:00
|
|
|
static const unsigned X86_GR16_AO_64[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
|
|
|
|
X86::R8W, X86::R9W, X86::R10W, X86::R11W,
|
|
|
|
X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
|
|
|
|
};
|
|
|
|
static const unsigned X86_GR16_AO_32[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
|
|
|
|
};
|
2006-09-08 08:48:29 +02:00
|
|
|
|
|
|
|
GR16Class::iterator
|
|
|
|
GR16Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 08:48:29 +02:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (Subtarget.is64Bit()) {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR16_AO_64_fp;
|
|
|
|
else
|
|
|
|
return X86_GR16_AO_64;
|
|
|
|
} else {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR16_AO_32_fp;
|
|
|
|
else
|
|
|
|
return X86_GR16_AO_32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-16 09:21:53 +02:00
|
|
|
GR16Class::iterator
|
2006-08-18 00:00:08 +02:00
|
|
|
GR16Class::allocation_order_end(const MachineFunction &MF) const {
|
2006-09-08 08:48:29 +02:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 08:48:29 +02:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (Subtarget.is64Bit()) {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
|
|
|
|
} else {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
|
|
|
|
}
|
2003-08-03 17:47:25 +02:00
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2006-09-08 08:48:29 +02:00
|
|
|
|
2006-05-16 09:21:53 +02:00
|
|
|
def GR32 : RegisterClass<"X86", [i32], 32,
|
2006-09-08 08:48:29 +02:00
|
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
|
2008-11-19 18:19:35 +01:00
|
|
|
R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
let SubRegClassList = [GR8, GR8, GR16];
|
2005-08-19 21:13:20 +02:00
|
|
|
let MethodProtos = [{
|
2006-09-08 08:48:29 +02:00
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
2006-08-18 00:00:08 +02:00
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
2005-08-19 21:13:20 +02:00
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
2009-01-27 20:25:38 +01:00
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate ESP or EBP.
|
|
|
|
static const unsigned X86_GR32_AO_64_fp[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
|
|
|
|
X86::R8D, X86::R9D, X86::R10D, X86::R11D,
|
|
|
|
X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D
|
|
|
|
};
|
|
|
|
static const unsigned X86_GR32_AO_32_fp[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX
|
|
|
|
};
|
2009-04-13 17:28:29 +02:00
|
|
|
// If not, just don't allocate ESP.
|
2009-01-27 20:25:38 +01:00
|
|
|
static const unsigned X86_GR32_AO_64[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
|
|
|
|
X86::R8D, X86::R9D, X86::R10D, X86::R11D,
|
|
|
|
X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
|
|
|
|
};
|
|
|
|
static const unsigned X86_GR32_AO_32[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP
|
|
|
|
};
|
2006-09-08 08:48:29 +02:00
|
|
|
|
|
|
|
GR32Class::iterator
|
|
|
|
GR32Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 08:48:29 +02:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (Subtarget.is64Bit()) {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR32_AO_64_fp;
|
|
|
|
else
|
|
|
|
return X86_GR32_AO_64;
|
|
|
|
} else {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR32_AO_32_fp;
|
|
|
|
else
|
|
|
|
return X86_GR32_AO_32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-16 09:21:53 +02:00
|
|
|
GR32Class::iterator
|
2006-08-18 00:00:08 +02:00
|
|
|
GR32Class::allocation_order_end(const MachineFunction &MF) const {
|
2006-09-08 08:48:29 +02:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2006-09-08 08:48:29 +02:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (Subtarget.is64Bit()) {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
|
|
|
|
} else {
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF))
|
2006-09-08 08:48:29 +02:00
|
|
|
return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
def GR64 : RegisterClass<"X86", [i64], 64,
|
|
|
|
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
|
2009-06-26 23:25:00 +02:00
|
|
|
RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
let SubRegClassList = [GR8, GR8, GR16, GR32];
|
2006-09-08 08:48:29 +02:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
GR64Class::iterator
|
|
|
|
GR64Class::allocation_order_end(const MachineFunction &MF) const {
|
2007-01-23 01:57:47 +01:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-02-10 19:45:23 +01:00
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
2008-03-11 08:16:00 +01:00
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return begin(); // None of these are allocatable in 32-bit.
|
2007-01-23 01:57:47 +01:00
|
|
|
if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
|
2009-06-26 23:25:00 +02:00
|
|
|
return end()-3; // If so, don't allocate RIP, RSP or RBP
|
2003-08-03 17:47:25 +02:00
|
|
|
else
|
2009-06-26 23:25:00 +02:00
|
|
|
return end()-2; // If not, just don't allocate RIP or RSP
|
2003-08-03 17:47:25 +02:00
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2006-09-08 08:48:29 +02:00
|
|
|
|
2009-04-27 18:41:36 +02:00
|
|
|
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
|
|
|
|
// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
|
|
|
|
// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
|
|
|
|
// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
|
|
|
|
// and GR64_ABCD are classes for registers that support 8-bit h-register
|
|
|
|
// operations.
|
|
|
|
def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
|
|
|
|
}
|
|
|
|
def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
}
|
2009-04-27 18:33:14 +02:00
|
|
|
def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
|
2009-04-27 18:41:36 +02:00
|
|
|
let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H];
|
2007-07-28 21:03:30 +02:00
|
|
|
}
|
2009-04-27 18:33:14 +02:00
|
|
|
def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
|
2009-04-27 18:41:36 +02:00
|
|
|
let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
}
|
2009-04-27 18:33:14 +02:00
|
|
|
def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
|
2009-04-27 18:41:36 +02:00
|
|
|
let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// GR8_NOREX, GR16_NOREX, GR32_NOREX, GR64_NOREX - Subclasses of
|
|
|
|
// GR8, GR16, GR32, and GR64 which contain only the first 8 GPRs.
|
|
|
|
// On x86-64, GR64_NOREX, GR32_NOREX and GR16_NOREX are the classes
|
|
|
|
// of registers which do not by themselves require a REX prefix.
|
|
|
|
def GR8_NOREX : RegisterClass<"X86", [i8], 8,
|
2009-04-15 02:00:48 +02:00
|
|
|
[AL, CL, DL, BL, AH, CH, DH, BH,
|
|
|
|
SIL, DIL, BPL, SPL]> {
|
2009-04-14 18:57:43 +02:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate SPL or BPL.
|
|
|
|
static const unsigned X86_GR8_NOREX_AO_64_fp[] = {
|
|
|
|
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL
|
|
|
|
};
|
|
|
|
// If not, just don't allocate SPL.
|
|
|
|
static const unsigned X86_GR8_NOREX_AO_64[] = {
|
|
|
|
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
|
|
|
|
};
|
|
|
|
// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
|
|
|
|
static const unsigned X86_GR8_NOREX_AO_32[] = {
|
2009-04-15 02:00:48 +02:00
|
|
|
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH
|
2009-04-14 18:57:43 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
GR8_NOREXClass::iterator
|
|
|
|
GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return X86_GR8_NOREX_AO_32;
|
|
|
|
else if (RI->hasFP(MF))
|
|
|
|
return X86_GR8_NOREX_AO_64_fp;
|
|
|
|
else
|
|
|
|
return X86_GR8_NOREX_AO_64;
|
|
|
|
}
|
|
|
|
|
|
|
|
GR8_NOREXClass::iterator
|
|
|
|
GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return X86_GR8_NOREX_AO_32 +
|
|
|
|
(sizeof(X86_GR8_NOREX_AO_32) / sizeof(unsigned));
|
|
|
|
else if (RI->hasFP(MF))
|
|
|
|
return X86_GR8_NOREX_AO_64_fp +
|
|
|
|
(sizeof(X86_GR8_NOREX_AO_64_fp) / sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR8_NOREX_AO_64 +
|
|
|
|
(sizeof(X86_GR8_NOREX_AO_64) / sizeof(unsigned));
|
|
|
|
}
|
|
|
|
}];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
}
|
|
|
|
def GR16_NOREX : RegisterClass<"X86", [i16], 16,
|
|
|
|
[AX, CX, DX, SI, DI, BX, BP, SP]> {
|
|
|
|
let SubRegClassList = [GR8_NOREX, GR8_NOREX];
|
2009-04-15 02:10:16 +02:00
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate SP or BP.
|
|
|
|
static const unsigned X86_GR16_AO_fp[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
|
|
|
|
};
|
|
|
|
// If not, just don't allocate SP.
|
|
|
|
static const unsigned X86_GR16_AO[] = {
|
|
|
|
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
|
|
|
|
};
|
|
|
|
|
|
|
|
GR16_NOREXClass::iterator
|
|
|
|
GR16_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
if (RI->hasFP(MF))
|
|
|
|
return X86_GR16_AO_fp;
|
|
|
|
else
|
|
|
|
return X86_GR16_AO;
|
|
|
|
}
|
|
|
|
|
|
|
|
GR16_NOREXClass::iterator
|
|
|
|
GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
if (RI->hasFP(MF))
|
|
|
|
return X86_GR16_AO_fp+(sizeof(X86_GR16_AO_fp)/sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR16_AO + (sizeof(X86_GR16_AO) / sizeof(unsigned));
|
|
|
|
}
|
|
|
|
}];
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 18:09:41 +02:00
|
|
|
}
|
|
|
|
// GR32_NOREX - GR32 registers which do not require a REX prefix.
|
|
|
|
def GR32_NOREX : RegisterClass<"X86", [i32], 32,
|
|
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
|
|
|
|
let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX];
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate ESP or EBP.
|
|
|
|
static const unsigned X86_GR32_NOREX_AO_fp[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX
|
|
|
|
};
|
|
|
|
// If not, just don't allocate ESP.
|
|
|
|
static const unsigned X86_GR32_NOREX_AO[] = {
|
|
|
|
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP
|
|
|
|
};
|
|
|
|
|
|
|
|
GR32_NOREXClass::iterator
|
|
|
|
GR32_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
if (RI->hasFP(MF))
|
|
|
|
return X86_GR32_NOREX_AO_fp;
|
|
|
|
else
|
|
|
|
return X86_GR32_NOREX_AO;
|
|
|
|
}
|
|
|
|
|
|
|
|
GR32_NOREXClass::iterator
|
|
|
|
GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
if (RI->hasFP(MF))
|
|
|
|
return X86_GR32_NOREX_AO_fp +
|
|
|
|
(sizeof(X86_GR32_NOREX_AO_fp) / sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR32_NOREX_AO +
|
|
|
|
(sizeof(X86_GR32_NOREX_AO) / sizeof(unsigned));
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
|
|
|
// GR64_NOREX - GR64 registers which do not require a REX prefix.
|
|
|
|
def GR64_NOREX : RegisterClass<"X86", [i64], 64,
|
|
|
|
[RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP]> {
|
|
|
|
let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
// Does the function dedicate RBP / EBP to being a frame ptr?
|
|
|
|
// If so, don't allocate RSP or RBP.
|
|
|
|
static const unsigned X86_GR64_NOREX_AO_fp[] = {
|
|
|
|
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX
|
|
|
|
};
|
|
|
|
// If not, just don't allocate RSP.
|
|
|
|
static const unsigned X86_GR64_NOREX_AO[] = {
|
|
|
|
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP
|
|
|
|
};
|
|
|
|
|
|
|
|
GR64_NOREXClass::iterator
|
|
|
|
GR64_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
if (RI->hasFP(MF))
|
|
|
|
return X86_GR64_NOREX_AO_fp;
|
|
|
|
else
|
|
|
|
return X86_GR64_NOREX_AO;
|
|
|
|
}
|
|
|
|
|
|
|
|
GR64_NOREXClass::iterator
|
|
|
|
GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
|
|
if (RI->hasFP(MF))
|
|
|
|
return X86_GR64_NOREX_AO_fp +
|
|
|
|
(sizeof(X86_GR64_NOREX_AO_fp) / sizeof(unsigned));
|
|
|
|
else
|
|
|
|
return X86_GR64_NOREX_AO +
|
|
|
|
(sizeof(X86_GR64_NOREX_AO) / sizeof(unsigned));
|
|
|
|
}
|
|
|
|
}];
|
2007-07-28 21:03:30 +02:00
|
|
|
}
|
2006-05-08 10:01:26 +02:00
|
|
|
|
2008-11-13 22:52:36 +01:00
|
|
|
// A class to support the 'A' assembler constraint: EAX then EDX.
|
2008-11-14 19:10:48 +01:00
|
|
|
def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>;
|
2008-11-13 22:52:36 +01:00
|
|
|
|
2005-12-20 23:59:51 +01:00
|
|
|
// Scalar SSE2 floating point registers.
|
|
|
|
def FR32 : RegisterClass<"X86", [f32], 32,
|
2006-09-08 08:48:29 +02:00
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
FR32Class::iterator
|
|
|
|
FR32Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2005-12-20 23:59:51 +01:00
|
|
|
def FR64 : RegisterClass<"X86", [f64], 64,
|
2006-09-08 08:48:29 +02:00
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
FR64Class::iterator
|
|
|
|
FR64Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
|
|
|
|
2005-06-27 23:20:31 +02:00
|
|
|
|
2004-12-02 19:17:31 +01:00
|
|
|
// FIXME: This sets up the floating point register files as though they are f64
|
|
|
|
// values, though they really are f80 values. This will cause us to spill
|
|
|
|
// values as 64-bit quantities instead of 80-bit quantities, which is much much
|
|
|
|
// faster on common hardware. In reality, this should be controlled by a
|
|
|
|
// command line option or something.
|
|
|
|
|
2008-03-10 22:08:41 +01:00
|
|
|
def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
|
|
|
def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
|
|
|
def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
2003-08-03 17:47:25 +02:00
|
|
|
|
2004-09-21 23:22:11 +02:00
|
|
|
// Floating point stack registers (these are not allocatable by the
|
|
|
|
// register allocator - the floating point stackifier is responsible
|
|
|
|
// for transforming FPn allocations to STn registers)
|
2008-03-10 22:08:41 +01:00
|
|
|
def RST : RegisterClass<"X86", [f80, f64, f32], 32,
|
2005-08-19 20:51:57 +02:00
|
|
|
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
|
2005-08-19 21:13:20 +02:00
|
|
|
let MethodProtos = [{
|
2006-08-18 00:00:08 +02:00
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
2005-08-19 21:13:20 +02:00
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
RSTClass::iterator
|
2006-08-18 00:00:08 +02:00
|
|
|
RSTClass::allocation_order_end(const MachineFunction &MF) const {
|
2004-09-21 23:22:11 +02:00
|
|
|
return begin();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
2006-02-20 23:34:53 +01:00
|
|
|
|
2006-02-21 02:38:21 +01:00
|
|
|
// Generic vector registers: VR64 and VR128.
|
2008-06-25 00:01:44 +02:00
|
|
|
def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64,
|
2006-02-21 02:38:21 +01:00
|
|
|
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
|
|
|
|
def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
|
2006-09-08 08:48:29 +02:00
|
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
|
|
|
let MethodProtos = [{
|
|
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
|
|
}];
|
|
|
|
let MethodBodies = [{
|
|
|
|
VR128Class::iterator
|
|
|
|
VR128Class::allocation_order_end(const MachineFunction &MF) const {
|
|
|
|
const TargetMachine &TM = MF.getTarget();
|
|
|
|
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
|
|
|
|
if (!Subtarget.is64Bit())
|
|
|
|
return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
|
|
|
|
else
|
|
|
|
return end();
|
|
|
|
}
|
|
|
|
}];
|
|
|
|
}
|
2009-06-30 00:50:51 +02:00
|
|
|
def VR256 : RegisterClass<"X86", [ v8i32, v4i64, v8f32, v4f64],256,
|
|
|
|
[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
|
|
|
|
YMM8, YMM9, YMM10, YMM11,
|
|
|
|
YMM12, YMM13, YMM14, YMM15]>;
|
2007-09-11 21:53:28 +02:00
|
|
|
|
|
|
|
// Status flags registers.
|
2007-09-19 03:36:39 +02:00
|
|
|
def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
|
|
|
|
let CopyCost = -1; // Don't allow copying of status registers.
|
|
|
|
}
|