Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.
The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.
llvm-svn: 132106
Use a proper worklist for use-def traversal without holding onto an
iterator. Now that we process all IV uses, we need complete logic for
resusing existing derived IV defs. See HoistStep.
llvm-svn: 132103
This doesn't change functionality (much), but it allows for a more fine-grained
eviction policy. The current policy only compares spill weights, and that is not
always the best thing to do. Spill weights are designed to serve linear scan,
and they don't consider live range splitting.
Add a mechanism so canEvict() can request that a live range be evicted and
split/spilled. This is to avoid infinite eviction loops.
llvm-svn: 132101
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
them.
I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.
llvm-svn: 132084
I kept the reference to the ABI since that is the common case. The
-fno-asynchronous-unwind-tables option is a user controlled way of breaking
the ABI.
llvm-svn: 132053
In file included from .../llvm/trunk/tools/lto/LTOCodeGenerator.cpp:45:
In file included from .../llvm/trunk/include/llvm/Support/system_error.h:225:
.../include/llvm/Config/config.h:591:9: warning: 'LLVM_PATH_XDOT_PY' macro redefined
#define LLVM_PATH_XDOT_PY ".../bin/xdot.py"
^
.../include/llvm/Config/llvm-config.h:98:9: note: previous definition is here
#define LLVM_PATH_XDOT_PY ""
^
1 warning generated.
(Paths edited for clarity)
Note: This only affected people who had xdot.py installed.
llvm-svn: 132050
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>
llvm-svn: 132041
case of a switch instruction. Back off this optimization when this would
eliminate all of the predecessors to the latch.
Sorry, I am unable to reduce a reasonably sized test case.
rdar://9486843
llvm-svn: 132022
Add a size alignment check to the .seh_stackalloc directive parser. Add a
more descriptive error message to the .seh_handler directive parser.
Add methods to the TargetAsmInfo struct in support of all this.
llvm-svn: 131992
