Cameron Zwarich
005920cae9
Rename a test to be more inclusive.
...
llvm-svn: 127765
2011-03-16 22:20:12 +00:00
Daniel Dunbar
8757b8c000
Revert r127757, "Patch to a fix dwarf relocation problem on ARM. One-line fix
...
plus the test where it used to break.", which broke Clang self-host of a
Debug+Asserts compiler, on OS X.
llvm-svn: 127763
2011-03-16 22:16:39 +00:00
Richard Osborne
8b90369d96
Add XCore intrinsics for setclk, setrdy.
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llvm-svn: 127761
2011-03-16 21:56:00 +00:00
Renato Golin
bf788a5626
Patch to a fix dwarf relocation problem on ARM. One-line fix plus the test where it used to break.
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llvm-svn: 127757
2011-03-16 21:05:52 +00:00
Cameron Zwarich
05eb0080d6
Add a test for i1 zeroext arguments on x86-64. We currently generate code that
...
conforms to the ABI, but DAGCombine could in theory recognize the sequence of
zext asserts and truncates and generate incorrect code.
llvm-svn: 127754
2011-03-16 20:15:44 +00:00
Richard Osborne
318e25c620
Add checkevent intrinsic to check if any resources owned by the current thread
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can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
NAKAMURA Takumi
7fd500c31d
test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32.
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llvm-svn: 127734
2011-03-16 13:53:07 +00:00
NAKAMURA Takumi
aa13f3550e
test/CodeGen/X86: Add a pattern for Win64.
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llvm-svn: 127733
2011-03-16 13:52:51 +00:00
NAKAMURA Takumi
e776f16e9d
test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They are useless to Win64 target.
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llvm-svn: 127732
2011-03-16 13:52:38 +00:00
NAKAMURA Takumi
bfbbe15937
test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet.
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llvm-svn: 127731
2011-03-16 13:52:20 +00:00
NAKAMURA Takumi
73a9789e43
test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize.
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llvm-svn: 127730
2011-03-16 13:52:08 +00:00
Bill Wendling
388dad6d62
Some minor cleanups based on feedback.
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llvm-svn: 127694
2011-03-15 20:47:26 +00:00
Evan Cheng
59ba6777c3
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
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llvm-svn: 127683
2011-03-15 18:41:52 +00:00
Richard Osborne
af1b66c427
On the XCore the scavenging slot should be closest to the SP.
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llvm-svn: 127680
2011-03-15 15:10:11 +00:00
Richard Osborne
70204c1c29
Add XCore intrinsics for getps, setps, setsr and clrsr.
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llvm-svn: 127678
2011-03-15 13:45:47 +00:00
Justin Holewinski
8948485aa7
PTX: Set PTX 2.0 as the minimum supported version
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- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions
llvm-svn: 127677
2011-03-15 13:24:15 +00:00
Evan Cheng
29faaebae9
Add a peephole optimization to optimize pairs of bitcasts. e.g.
...
v2 = bitcast v1
...
v3 = bitcast v2
...
= v3
=>
v2 = bitcast v1
...
= v1
if v1 and v3 are of in the same register class.
bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.
rdar://9104514
llvm-svn: 127668
2011-03-15 05:13:13 +00:00
Evan Cheng
bac3e87eaa
sext(undef) = 0, because the top bits will all be the same.
...
zext(undef) = 0, because the top bits will be zero.
llvm-svn: 127649
2011-03-15 02:22:10 +00:00
Bill Wendling
713c4bc3ee
Testcase for r127630.
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llvm-svn: 127648
2011-03-15 01:49:08 +00:00
Jim Grosbach
3de97c6e32
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
...
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
llvm-svn: 127637
2011-03-15 00:30:40 +00:00
Bill Wendling
da1364d669
Generate a VTBL instruction instead of a series of loads and stores when we
...
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
llvm-svn: 127630
2011-03-14 23:02:38 +00:00
Eric Christopher
8180806e0f
Fix this test up a bit.
...
llvm-svn: 127621
2011-03-14 21:05:21 +00:00
Evan Cheng
cb70b9e80b
Minor optimization. sign-ext/anyext of undef is still undef.
...
llvm-svn: 127598
2011-03-14 18:15:55 +00:00
Justin Holewinski
a2f7c8557c
PTX: Emit global arrays with proper sizes
...
- Emit all arrays as type .b8 and proper sizes in bytes to conform
to the output of nvcc
llvm-svn: 127584
2011-03-14 15:40:11 +00:00
Justin Holewinski
995d10cfea
PTX: Add support for sqrt/sin/cos intrinsics
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llvm-svn: 127578
2011-03-14 14:09:33 +00:00
Che-Liang Chiou
6ff0aa8ab3
ptx: add set.p instruction and related changes to predicate execution
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llvm-svn: 127577
2011-03-14 11:26:01 +00:00
Eric Christopher
392d8f7d08
Saving files before committing is overrated.
...
Add a RUN line to this test.
llvm-svn: 127520
2011-03-12 01:36:23 +00:00
Eric Christopher
80a45901e0
Sometimes isPredicable lies to us and tells us we don't need the operands.
...
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
Jim Grosbach
27eaca3e0d
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
...
effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Cameron Zwarich
bf5c9cd119
Roll r127459 back in:
...
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127498
2011-03-11 21:52:04 +00:00
Cameron Zwarich
39a49276db
Fix the GCC test suite issue exposed by r127477, which was caused by stack
...
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.
llvm-svn: 127497
2011-03-11 21:51:56 +00:00
Daniel Dunbar
a02706c889
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
...
created from the", it broke some GCC test suite tests.
llvm-svn: 127477
2011-03-11 19:30:30 +00:00
Cameron Zwarich
9ed726c151
Optimize trivial branches in CodeGenPrepare, which often get created from the
...
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127459
2011-03-11 04:54:27 +00:00
Eric Christopher
46f43c9cce
Change the x86 32-bit scheduler to register pressure and fix up the
...
corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
llvm-svn: 127441
2011-03-11 01:05:58 +00:00
Evan Cheng
d5d2d4a158
Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
...
llvm-svn: 127440
2011-03-11 00:48:56 +00:00
Jim Grosbach
1986d9ac8f
Properly pseudo-ize MOVCCr and MOVCCs.
...
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Justin Holewinski
a26d2f782e
PTX: Add preliminary support for floating-point divide and multiply-and-add
...
llvm-svn: 127410
2011-03-10 16:57:18 +00:00
Che-Liang Chiou
fc6c7ba9d5
ptx: add the rest of special registers of ISA version 2.0
...
llvm-svn: 127397
2011-03-10 04:05:57 +00:00
Stuart Hastings
fd42046d56
Revert 127359; it broke lencod.
...
llvm-svn: 127382
2011-03-10 00:25:53 +00:00
Daniel Dunbar
11a8b6c4ff
Revert "Re-enable test and hope to silence the buildbots", still broken.
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llvm-svn: 127369
2011-03-09 22:48:46 +00:00
Benjamin Kramer
8313cf1cf4
Fix mistyped CHECK lines.
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llvm-svn: 127366
2011-03-09 22:07:31 +00:00
Stuart Hastings
6c99b422b1
Tweak test to work on Linux.
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llvm-svn: 127364
2011-03-09 21:35:10 +00:00
Stuart Hastings
5c555821bb
Disable this test temporarily to reduce BuildBot complaints.
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llvm-svn: 127363
2011-03-09 21:33:47 +00:00
Stuart Hastings
61f9a3dab2
X86 byval copies no longer always_inline. <rdar://problem/8706628>
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llvm-svn: 127359
2011-03-09 21:10:30 +00:00
Bruno Cardoso Lopes
f34376b0e1
Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka
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llvm-svn: 127358
2011-03-09 21:05:32 +00:00
Bruno Cardoso Lopes
51df3638f8
Re-enable test and hope to silence the buildbots
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llvm-svn: 127357
2011-03-09 21:00:16 +00:00
Bruno Cardoso Lopes
64f0169989
try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka.
...
llvm-svn: 127356
2011-03-09 20:59:05 +00:00
Jakob Stoklund Olesen
4d0c9d0af7
Make physreg coalescing independent on the number of uses of the virtual register.
...
The damage done by physreg coalescing only depends on the number of instructions
the extended physreg live range covers. This fixes PR9438.
The heuristic is still luck-based, and physreg coalescing really should be
disabled completely. We need a register allocator with better hinting support
before that is possible.
Convert a test to FileCheck and force spilling by inserting an extra call. The
previous spilling behavior was dependent on misguided physreg coalescing
decisions.
llvm-svn: 127351
2011-03-09 19:27:06 +00:00
Jakob Stoklund Olesen
10d5d5d25c
Delete a test case that is very sensitive to coalescer behavior.
...
The test is derived from an old miscompilation of
MultiSource/Benchmarks/VersaBench/8b10b which is run regularly, so we are not
losing coverage.
llvm-svn: 127350
2011-03-09 19:27:02 +00:00
Bruno Cardoso Lopes
88bef593d8
Improve varags handling, with testcases. Patch by Sasa Stankovic
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llvm-svn: 127349
2011-03-09 19:22:22 +00:00