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04c0915a2f
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918 Commits

Author SHA1 Message Date
Evan Cheng
04c0915a2f Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. 
llvm-svn: 51667
 2008-05-29 08:22:04 +00:00
Evan Cheng
f2e38956ff Add nounwind. 
llvm-svn: 51665
 2008-05-29 07:09:24 +00:00
Evan Cheng
cd45b11bc1 Fix PR2289: vr defined by multiple implicit_def as result of coalescing. 
llvm-svn: 51648
 2008-05-28 17:40:10 +00:00
Evan Cheng
591b57edd6 Teach local register allocator to deal with landing pad MBB's. 
llvm-svn: 51647
 2008-05-28 17:22:32 +00:00
Dan Gohman
568685ffa7 Specify a target so that this tests tests what it's intended to test. 
llvm-svn: 51600
 2008-05-27 17:55:57 +00:00
Dan Gohman
3ba9d77adb Make this test independent of the target-triple; the stack alignment 
is specifically what this test depends on.

llvm-svn: 51599
 2008-05-27 17:44:23 +00:00
Nick Lewycky
c096899392 The Linux ABI emits an extra "movl %esp, %ebp" in function prologue and 
sometimes a "mov %ebp, %esp" in the epilogue.

Force these tests that rely on counting 'mov' to use i686-apple-darwin8.8.0
where they were written.

llvm-svn: 51568
 2008-05-26 20:18:56 +00:00
Evan Cheng
e9c1c96f7b New loadl_pd and loadh_pd tests. 
llvm-svn: 51525
 2008-05-24 00:10:02 +00:00
Evan Cheng
4f660778f0 Use movlps / movhps to modify low / high half of 16-byet memory location. 
llvm-svn: 51501
 2008-05-23 21:23:16 +00:00
Dan Gohman
6cc0b4f262 Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add 
load-folding table entries for PMULDQ and PMULLD.

llvm-svn: 51489
 2008-05-23 17:49:40 +00:00
Evan Cheng
097e95b1f7 Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks. 
Also fixed some 80 col. violations.

llvm-svn: 51462
 2008-05-23 00:37:07 +00:00
Evan Cheng
dc3a3d3a2c Add a couple of test cases. 
llvm-svn: 51441
 2008-05-22 21:19:19 +00:00
Evan Cheng
d1373cd497 Add missing patterns. 
llvm-svn: 51435
 2008-05-22 18:56:56 +00:00
Chris Lattner
6a45cf9dd6 Add support for multiple-return values in inline asm. This should 
get inline asm working as well as it did previously with the CBE
with the new MRV support for inline asm.

llvm-svn: 51420
 2008-05-22 06:19:37 +00:00
Chris Lattner
477239c56d testcase for PR2267 
llvm-svn: 51408
 2008-05-22 04:45:22 +00:00
Evan Cheng
8e02953de8 Fix PR2343. An *interesting* coalescer bug. 
BB1:                                                                                                                                                  
  vr1025 = copy vr1024                                                                                                                                
  ..                                                                                                                                                  
BB2:                                                                                                                                                  
  vr1024 = op                                                                                                                                         
         = op vr1025                                                                                                                                     
  <loop eventually branch back to BB1>

Even though vr1025 is copied from vr1024, it's not safe to coalesced them since live range of vr1025 intersects the def of vr1024. This happens when vr1025 is assigned the value of the previous iteration of vr1024 in the loop.

llvm-svn: 51394
 2008-05-21 22:34:12 +00:00
Gabor Greif
b03785f0cd Eliminate questionable syntax for stdin redirection. This probably also speeds things up a bit. 
llvm-svn: 51357
 2008-05-20 22:07:21 +00:00
Gabor Greif
807c2df887 sabre brings to my attention that the 'tr' suffix is also obsolete 
llvm-svn: 51349
 2008-05-20 21:00:03 +00:00
Gabor Greif
d8a4dbb5da Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too. 
llvm-svn: 51328
 2008-05-20 19:52:04 +00:00
Evan Cheng
55e3957c96 More local spiller complexity! 
If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.

llvm-svn: 51306
 2008-05-20 08:13:21 +00:00
Evan Cheng
408425f0e0 Don't spill dead def. 
llvm-svn: 51305
 2008-05-20 08:10:37 +00:00
Dan Gohman
7681889f75 Run vortex-bug as x86-64, which is what the original bug was triggered on. 
llvm-svn: 51289
 2008-05-20 00:54:39 +00:00
Dale Johannesen
4e46c5601d Use common where we mean common, not weak. 
llvm-svn: 51173
 2008-05-16 00:52:30 +00:00
Dan Gohman
2da4145cd8 Fix a bug in LoopStrengthReduce that caused it to emit IR with 
use-before-def. The problem comes up in code with multiple PHIs where
one PHI is being rewritten in terms of the other, but the other needs
to be casted first. LLVM rules requre the cast instruction to be
inserted after any PHI instructions, but when instructions were
inserted to replace the second PHI value with a function of the first,
they were ended up going before the cast instruction. Avoid this
problem by remembering the location of the cast instruction, when one
is needed, and inserting the expansion of the new value after it.

This fixes a bug that surfaced in 255.vortex on x86-64 when
instcombine was removed from the middle of the loop optimization
passes. 

llvm-svn: 51169
 2008-05-15 23:26:57 +00:00
Dan Gohman
cd29e1fa60 When bit-twiddling CondCode values for integer comparisons produces 
SETOEQ, is it does with (SETEQ & SETULE), map it to SETEQ.

llvm-svn: 51112
 2008-05-14 18:17:09 +00:00
Evan Cheng
9e15622879 Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset. 
pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax

llvm-svn: 51026
 2008-05-13 08:35:03 +00:00
Evan Cheng
e4ee4c2870 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. 
llvm-svn: 51019
 2008-05-13 00:54:02 +00:00
Evan Cheng
fcbdc8bd6e Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other. 
llvm-svn: 51008
 2008-05-12 23:04:07 +00:00
Dale Johannesen
b54491d31a New test for tail merging 
llvm-svn: 51007
 2008-05-12 22:59:44 +00:00
Evan Cheng
c19c639ad7 When transforming a vector_shuffle to a load, the base address must not be an undef. 
llvm-svn: 50940
 2008-05-10 06:46:49 +00:00
Evan Cheng
fc4b8e1d96 Add nounwind. 
llvm-svn: 50931
 2008-05-10 02:22:25 +00:00
Evan Cheng
cf4d5567d5 If all sources of a PHI node are defined by an implicit_def, just emit an implicit_def instead of a copy. 
llvm-svn: 50927
 2008-05-10 00:17:50 +00:00
Evan Cheng
2adea48f7e Add a pattern to do move the low element of a v4f32 and zero extend the rest. 
llvm-svn: 50922
 2008-05-09 23:37:55 +00:00
Evan Cheng
3493e43afd Handle a few more cases of folding load i64 into xmm and zero top bits. 
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.

llvm-svn: 50918
 2008-05-09 21:53:03 +00:00
Evan Cheng
a0688bf1cb Simplify test. 
llvm-svn: 50911
 2008-05-09 19:56:32 +00:00
Evan Cheng
f824b47188 Use movq to move low half of XMM register and zero-extend the rest. 
llvm-svn: 50874
 2008-05-08 22:35:02 +00:00
Evan Cheng
f97e716511 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. 
llvm-svn: 50838
 2008-05-08 00:57:18 +00:00
Evan Cheng
7ff000c175 Add nounwind. 
llvm-svn: 50837
 2008-05-07 22:59:08 +00:00
Evan Cheng
c86c035346 Yet another nasty spiller bug. 
%ecx = op
store %cl<kill>, (addr)
(addr) = op %al

It's not safe to unfold the last operand and eliminate store even though %cl is marked kill. It's a sub-register use which means one of its super-register(s) may be used below.

llvm-svn: 50794
 2008-05-07 00:49:28 +00:00
Anton Korobeynikov
a9ff11ea5f Use target triple in tests, not 'realign-stack=0' option. Per request. 
llvm-svn: 50778
 2008-05-06 23:09:29 +00:00
Evan Cheng
a84ed06284 Fix PR2287. Darwin passes mmx values in register in 64-mode, not Linux. 
llvm-svn: 50716
 2008-05-06 07:23:50 +00:00
Mon P Wang
84a269e023 Added addition atomic instrinsics and, or, xor, min, and max. 
llvm-svn: 50663
 2008-05-05 19:05:59 +00:00
Chris Lattner
ca94848f66 no need for eh info 
llvm-svn: 50658
 2008-05-05 18:24:33 +00:00
Dan Gohman
c860d9c77c Add AsmPrinter support for emitting a directive to declare that 
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634
 2008-05-05 00:28:39 +00:00
Evan Cheng
a7747df955 Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register. 
llvm-svn: 50619
 2008-05-04 09:15:50 +00:00
Evan Cheng
c1c2adbfc6 Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. 
llvm-svn: 50601
 2008-05-03 00:52:09 +00:00
Chris Lattner
8cc3e89b87 specify an arch for non-x86 hosts. 
llvm-svn: 50576
 2008-05-02 15:11:58 +00:00
Bill Wendling
81b5245cec Adding testcase. 
llvm-svn: 50536
 2008-05-01 18:41:09 +00:00
Chris Lattner
e9bbe8e6b6 don't randomly miscompile seto/setuo just because we are in 
ffastmath mode.  This fixes rdar://5902801, a miscompilation
of gcc.dg/builtins-8.c.

Bill, please pull this into Tak.

llvm-svn: 50523
 2008-05-01 07:26:11 +00:00
Arnold Schwaighofer
29a654857a Really commit the test checking the argument lowering behaviour on x86-64 :). 
llvm-svn: 50478
 2008-04-30 09:19:47 +00:00