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102 Commits

Author SHA1 Message Date
Benjamin Kramer
0c823ae0ed Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Craig Topper
55b5aa4042 Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended. 
llvm-svn: 157122
 2012-05-19 19:14:18 +00:00
Jim Grosbach
2e62e2f664 Allow MCCodeEmitter access to the target MCRegisterInfo. 
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
 2012-05-15 17:35:52 +00:00
Hans Wennborg
a5a417fcd3 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

llvm-svn: 156611
 2012-05-11 10:11:01 +00:00
Jim Grosbach
f7461026c2 Nuke a few dead remnants of the CBE. 
llvm-svn: 156241
 2012-05-05 17:45:12 +00:00
Pete Cooper
584ad8ab86 Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT emitter. Needs some major refactoring as these two code emitters are almost identical 
llvm-svn: 155810
 2012-04-30 03:56:44 +00:00
NAKAMURA Takumi
1bfc716b7d Target/X86/MCTargetDesc/X86MCAsmInfo.cpp: Enable DwarfCFI (aka DW2) on Cygming. 
Cygwin-1.7 supports dw2. Some recent mingw distros support one, too.
I have confirmed test-suite/SingleSource/Benchmarks/Shootout-C++/except.cpp can pass on Cygwin.

llvm-svn: 154247
 2012-04-07 02:24:20 +00:00
Craig Topper
dbc259a436 Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. 
llvm-svn: 153860
 2012-04-02 06:09:36 +00:00
Craig Topper
bf6a47d0ec Prune some includes 
llvm-svn: 153502
 2012-03-27 07:54:11 +00:00
Joerg Sonnenberger
4df2738e5f Put Is64BitMemOperand into !defined(NDEBUG) for now. 
llvm-svn: 153185
 2012-03-21 14:09:26 +00:00
Joerg Sonnenberger
82af1c8704 Fix generation of the address size override prefix. Add assertions for 
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.

llvm-svn: 153166
 2012-03-21 05:48:07 +00:00
Craig Topper
b1f171a213 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
llvm-svn: 152997
 2012-03-17 18:46:09 +00:00
Jim Grosbach
2eea383b12 Make MCRegisterInfo available to the the MCInstPrinter. 
Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043
 2012-03-05 19:33:20 +00:00
Michael J. Spencer
0eb4a851f6 Minimal changes for LLVM to compile under VS11. 
llvm-svn: 151849
 2012-03-01 22:42:52 +00:00
Craig Topper
cfbfa3dcd1 Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Craig Topper
ecf21d8132 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Anton Korobeynikov
5996573d4b Add support for implicit TLS model used with MS VC runtime. 
Patch by Kai Nacke!

llvm-svn: 150307
 2012-02-11 17:26:53 +00:00
Craig Topper
dfa8617ab9 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Craig Topper
fe4a950689 Convert assert(0) to llvm_unreachable in X86 Target directory. 
llvm-svn: 149809
 2012-02-05 05:38:58 +00:00
Evan Cheng
111c0844d5 PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina. 
llvm-svn: 149294
 2012-01-30 23:10:32 +00:00
Jim Grosbach
e6ac20aadf Keep source location information for X86 MCFixup's. 
llvm-svn: 149106
 2012-01-27 00:51:27 +00:00
David Blaikie
06ecc99a56 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Jim Grosbach
f88f0b08c4 Tidy up. MCAsmBackend naming conventions. 
llvm-svn: 148400
 2012-01-18 18:52:16 +00:00
Craig Topper
44a5136fac Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
llvm-svn: 147366
 2011-12-30 04:48:54 +00:00
Rafael Espindola
504588a7a3 Section relative fixups are a coff concept, not a x86 one. Replace the 
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.

llvm-svn: 147252
 2011-12-24 14:47:52 +00:00
Rafael Espindola
2fc741dfac Move x86 specific bits of the COFF writer to lib/Target/X86. 
llvm-svn: 147231
 2011-12-24 02:14:02 +00:00
Rafael Espindola
8c9b0dea02 Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

llvm-svn: 147060
 2011-12-21 17:30:17 +00:00
Rafael Espindola
f9c7f9e3f3 Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059
 2011-12-21 17:00:36 +00:00
David Blaikie
576aba04f1 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
llvm-svn: 146960
 2011-12-20 02:50:00 +00:00
Rafael Espindola
549d0683b1 Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

llvm-svn: 146801
 2011-12-17 01:14:52 +00:00
Daniel Dunbar
30d6a45140 LLVMBuild: Remove trailing newline, which irked me. 
llvm-svn: 146409
 2011-12-12 19:48:00 +00:00
Jan Sjödin
b4602e048f XOP encoding bits and logic. 
llvm-svn: 146397
 2011-12-12 19:12:26 +00:00
Rafael Espindola
9b9d35cc05 Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas 
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311
 2011-12-10 02:28:43 +00:00
Jan Sjödin
fb32802944 Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding. 
llvm-svn: 146151
 2011-12-08 14:43:19 +00:00
Jim Grosbach
633ce3426c Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881
 2011-12-06 00:47:03 +00:00
Daniel Dunbar
4e00f5f8fd build/CMake: Finish removal of add_llvm_library_dependencies. 
llvm-svn: 145420
 2011-11-29 19:25:30 +00:00
Michael J. Spencer
5fade79478 MC/X86/COFF: Allow quotes in names when targeting MS/Windows, 
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

llvm-svn: 145409
 2011-11-29 18:00:06 +00:00
Bruno Cardoso Lopes
626d04cc6f This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
 2011-11-25 19:33:42 +00:00
Evan Cheng
2b239cbcf6 Sink codegen optimization level into MCCodeGenInfo along side relocation model 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
 2011-11-16 08:38:26 +00:00
Daniel Dunbar
73d41b0f03 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

llvm-svn: 144444
 2011-11-12 02:10:57 +00:00
Daniel Dunbar
3760ebeebb build: Add initial cut at LLVMBuild.txt files. 
llvm-svn: 143634
 2011-11-03 18:53:17 +00:00
Craig Topper
0e63b4485c Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
David Meyer
c50cb2f15a Remove NaClMode 
llvm-svn: 142338
 2011-10-18 05:29:23 +00:00
Craig Topper
29c4a473d0 Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. 
llvm-svn: 142177
 2011-10-17 05:33:10 +00:00
Craig Topper
6c900d9810 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper
2cd868184c Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper
4c6357d4af Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper
dab0c92a4f Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. 
llvm-svn: 142089
 2011-10-16 00:21:51 +00:00
Craig Topper
62e63d9bb9 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00