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Commit Graph

95550 Commits

Author SHA1 Message Date
Andrew Trick
0d8da69006 mi-sched: cleanup register pressure update, remove a FIXME.
llvm-svn: 190181
2013-09-06 17:32:47 +00:00
Andrew Trick
2792f17795 mi-sched: improve regpressure tracing.
llvm-svn: 190180
2013-09-06 17:32:44 +00:00
Andrew Trick
6f423c533c mi-sched: print tree size in -view-misched-dags
llvm-svn: 190179
2013-09-06 17:32:42 +00:00
Andrew Trick
735ce8c85e mi-sched: register pressure update tracing.
llvm-svn: 190178
2013-09-06 17:32:39 +00:00
Andrew Trick
0c6ae850b7 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases.

llvm-svn: 190177
2013-09-06 17:32:36 +00:00
Andrew Trick
bf56e1926d Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

llvm-svn: 190176
2013-09-06 17:32:34 +00:00
Hans Wennborg
5265ac9dbf msbuild integration: provide separate files for VS2010 and VS2012
The previous msbuild integration only worked if VS2010 was installed. This patch
renames the current integration to LLVM-vs2010 and adds LLVM-vs2012.

Differential Revision: http://llvm-reviews.chandlerc.com/D1614

llvm-svn: 190173
2013-09-06 17:05:46 +00:00
Matthias Braun
667850a4b2 avoid unnecessary direct access to LiveInterval::ranges
llvm-svn: 190170
2013-09-06 16:44:32 +00:00
Matthias Braun
c8c6a4ff0d remove unused argument from LiveRanges::join()
llvm-svn: 190169
2013-09-06 16:44:29 +00:00
Matthias Braun
df0ba22e8a remove pointless assert
The if above it ensures the property anyway.

llvm-svn: 190168
2013-09-06 16:44:27 +00:00
Matthias Braun
3de3ef9ed7 fix comment
There's no 'B3' in the example.

llvm-svn: 190167
2013-09-06 16:44:25 +00:00
Matthias Braun
15fb34e896 fix typo in comment
llvm-svn: 190165
2013-09-06 16:19:22 +00:00
Daniel Sanders
10a7da8f65 [mips][msa] Indentation
llvm-svn: 190156
2013-09-06 13:25:06 +00:00
Daniel Sanders
11008ea159 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
2013-09-06 13:15:05 +00:00
Vladimir Medic
d17f16c84f This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Daniel Sanders
22d0137a75 [mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
2013-09-06 13:01:47 +00:00
Vladimir Medic
c122b6c139 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Daniel Sanders
0eb9e53280 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
2013-09-06 12:50:52 +00:00
Daniel Sanders
cb68899283 [mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
2013-09-06 12:44:13 +00:00
Vladimir Medic
a00506588f This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Tim Northover
5e921518f7 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

llvm-svn: 190147
2013-09-06 12:38:12 +00:00
Daniel Sanders
d9577fe859 [mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
2013-09-06 12:32:57 +00:00
Daniel Sanders
6089833291 [mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
2013-09-06 12:30:43 +00:00
Vladimir Medic
0c18f0f6ce This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Daniel Sanders
e8f95344a5 [mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
2013-09-06 12:28:13 +00:00
Daniel Sanders
5e6aa9c0b4 [mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
2013-09-06 12:25:47 +00:00
Daniel Sanders
caabc263f0 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
2013-09-06 12:23:19 +00:00
Daniel Sanders
e90f0ba299 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
2013-09-06 12:10:24 +00:00
Richard Sandiford
8d6edc5218 [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.

llvm-svn: 190138
2013-09-06 11:51:39 +00:00
Daniel Sanders
66131ccd3e [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change

llvm-svn: 190134
2013-09-06 11:01:38 +00:00
Daniel Sanders
d571ce1dd4 [mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133
2013-09-06 10:59:24 +00:00
Daniel Sanders
87992178d5 [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change

llvm-svn: 190131
2013-09-06 10:55:15 +00:00
Richard Sandiford
ea5b4917b9 [SystemZ] Use XC for a memset of 0
llvm-svn: 190130
2013-09-06 10:25:07 +00:00
Matt Arsenault
4c2083b14a Use type helper functions.
llvm-svn: 190113
2013-09-06 00:37:24 +00:00
Matt Arsenault
f658af2617 Teach CodeGenPrepare about address spaces
llvm-svn: 190112
2013-09-06 00:18:43 +00:00
Tom Stellard
0aa46c444e R600: Coding style
llvm-svn: 190110
2013-09-05 23:55:13 +00:00
Juergen Ributzka
4554c8ed29 [X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.

This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.

Reviewer: Nadav
llvm-svn: 190105
2013-09-05 23:02:56 +00:00
Kevin Enderby
d37af1a3b4 Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment.  In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.

rdar://9356266

llvm-svn: 190096
2013-09-05 20:25:06 +00:00
Matt Arsenault
f022cb3c1a Consistently use dbgs() in debug printing
llvm-svn: 190093
2013-09-05 19:48:28 +00:00
Manman Ren
fb2230d917 Trying to un-break the bots.
llvm-svn: 190092
2013-09-05 19:44:52 +00:00
Matt Arsenault
071be273be R600: Fix i64 to i32 trunc on SI
llvm-svn: 190091
2013-09-05 19:41:10 +00:00
Rafael Espindola
5a6f92c702 Remove unused argument.
llvm-svn: 190090
2013-09-05 19:15:21 +00:00
Yunzhong Gao
9c0a894c6d Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.

The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289

llvm-svn: 190089
2013-09-05 19:14:26 +00:00
Manman Ren
01c483fca6 Debug Info: Use identifier to reference DIType in base type field of
ptr_to_member.

We introduce a new class DITypeRef that represents a reference to a DIType.
It wraps around a Value*, which can be either an identifier in MDString
or an actual MDNode. The class has a helper function "resolve" that
finds the actual MDNode for a given DITypeRef.

We specialize getFieldAs to return a field that is a reference to a
DIType. To correctly access the base type field of ptr_to_member,
getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef.

Also add a typedef for DITypeIdentifierMap and a helper
generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep
a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually
populate the map.

Verifier is updated accordingly.

llvm-svn: 190081
2013-09-05 18:48:31 +00:00
Tom Stellard
ce0432a0c3 R600: Add support for local memory atomic add
llvm-svn: 190080
2013-09-05 18:38:09 +00:00
Tom Stellard
6c1db18560 R600: Expand SELECT nodes rather than custom lowering them
llvm-svn: 190079
2013-09-05 18:38:03 +00:00
Tom Stellard
8f7c5a681a R600: Fix incorrect LDS size calculation
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.

llvm-svn: 190078
2013-09-05 18:37:57 +00:00
Tom Stellard
d2fff2dd99 R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
llvm-svn: 190077
2013-09-05 18:37:52 +00:00
Tom Stellard
b258da41d8 R600: Fix segfault in R600TextureIntrinsicReplacer
This pass was segfaulting when it ran into a non-intrinsic function
call.  Function calls are not supported, so now instead of segfaulting,
we will get an assertion failure with a nice error message.

I'm not sure how to test this using lit.

llvm-svn: 190076
2013-09-05 18:37:45 +00:00
Eric Christopher
059d9c3395 Move accelerator table defines and constants to Dwarf.h since
we're proposing it for DWARF5.

No functional change intended.

llvm-svn: 190074
2013-09-05 18:20:16 +00:00