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Commit Graph

640 Commits

Author SHA1 Message Date
Evan Cheng
157d40fba1 Hide the call to InitMCInstrInfo into tblgen generated ctor.
llvm-svn: 134244
2011-07-01 17:57:27 +00:00
Akira Hatanaka
960f6898a6 Improve Mips back-end's handling of DBG_VALUE.
llvm-svn: 134224
2011-07-01 01:04:43 +00:00
Evan Cheng
034261674b Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
2011-06-30 01:53:36 +00:00
Eric Christopher
f04ac137f3 Update comment for getRegForInlineAsmConstraint for Mips.
llvm-svn: 134087
2011-06-29 19:33:04 +00:00
Eric Christopher
82c3bcfb14 Remove getRegClassForInlineAsmConstraint for Mips.
Part of rdar://9643582

llvm-svn: 134084
2011-06-29 19:04:31 +00:00
Evan Cheng
b4dc8bdd22 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
llvm-svn: 134049
2011-06-29 01:14:12 +00:00
Evan Cheng
65e7766262 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
llvm-svn: 134030
2011-06-28 21:14:33 +00:00
Evan Cheng
b83b307ae8 Hide more details in tablegen generated MCRegisterInfo ctor function.
llvm-svn: 134027
2011-06-28 20:44:22 +00:00
Evan Cheng
a115f77785 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
llvm-svn: 134024
2011-06-28 20:07:07 +00:00
Evan Cheng
4a169be530 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng
6fea701360 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
2011-06-27 18:32:37 +00:00
Akira Hatanaka
539ba34c25 Change the chain input of nodes that load the address of a function. This change
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
2011-06-24 19:01:25 +00:00
Akira Hatanaka
3a3e7dfd84 Prevent generation of redundant addiu instructions that compute address of
static variables or functions. 

llvm-svn: 133803
2011-06-24 17:55:19 +00:00
Evan Cheng
e0801b07e0 Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
2011-06-24 01:44:41 +00:00
Akira Hatanaka
288c049012 Add A0 and A1 to the list of registers used for returning a value in order to
handle functions with return type Complex long long.

llvm-svn: 133497
2011-06-21 01:28:11 +00:00
Akira Hatanaka
1197db1f9b Coding style fixes.
llvm-svn: 133496
2011-06-21 01:02:03 +00:00
Akira Hatanaka
1e08980a21 Re-apply 132758 and 132768 which were speculatively reverted in 132777.
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
Bruno Cardoso Lopes
762b3d1f0f Silence warnings in non assert builds. Patch by David Blaikie
llvm-svn: 133118
2011-06-16 00:40:02 +00:00
Jakob Stoklund Olesen
d89900e14c Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
2011-06-15 23:28:14 +00:00
Jakob Stoklund Olesen
164dc685e5 Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781
2011-06-09 16:56:59 +00:00
Eric Christopher
24dafa3dbc Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
Akira Hatanaka
33ec063f3b Initial support for inline asm memory operand constraints.
llvm-svn: 132768
2011-06-09 03:31:05 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965

llvm-svn: 132763
2011-06-08 23:55:35 +00:00
Akira Hatanaka
38115eb019 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
dynamically allocated stack area was not set.

llvm-svn: 132758
2011-06-08 21:28:09 +00:00
Akira Hatanaka
ea8ce56dbb Reorganize code in MipsTargetLowering::LowerCall to improve readability.
llvm-svn: 132756
2011-06-08 17:39:33 +00:00
Akira Hatanaka
101d50423a Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
llvm-svn: 132726
2011-06-07 19:28:39 +00:00
Akira Hatanaka
e56d1fa083 Put back removed line.
llvm-svn: 132725
2011-06-07 19:03:14 +00:00
Akira Hatanaka
3b7982650c Coding style fixes.
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
2011-06-07 18:58:42 +00:00
Akira Hatanaka
f56f544d80 Use tabs to separate opcode and operand strings.
llvm-svn: 132718
2011-06-07 18:16:51 +00:00
Akira Hatanaka
fe54bb9de1 Add comments for wrapper node patterns in MipsInstrInfo.td.
llvm-svn: 132717
2011-06-07 18:00:14 +00:00
Akira Hatanaka
fbeb14925f Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703
2011-06-07 02:17:21 +00:00
Akira Hatanaka
1f91013bcb Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
llvm-svn: 132448
2011-06-02 01:03:14 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
llvm-svn: 132444
2011-06-02 00:24:44 +00:00
Bruno Cardoso Lopes
9231127d37 Fix uninitialized variables and silence warnings
llvm-svn: 132355
2011-05-31 20:25:26 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
2011-05-31 02:53:58 +00:00
Rafael Espindola
33f7d7f9fa Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

llvm-svn: 132317
2011-05-30 20:20:15 +00:00
Rafael Espindola
51a8fe13bc Remove the dwarf numbers from the D registers. They don't have dwarf numbers
and should probably be encoded as

DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33

llvm-svn: 132274
2011-05-29 02:21:01 +00:00
Akira Hatanaka
45b3f52c41 Change the set of callee-saved registers for non-MIPS32 architectures specified
in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.

 

llvm-svn: 132243
2011-05-28 01:41:05 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.).
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
2011-05-28 01:07:07 +00:00
Akira Hatanaka
71839b355d Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
a function has any function calls.

llvm-svn: 132140
2011-05-26 20:30:31 +00:00
Rafael Espindola
a77d692299 Fix some dwarf register numbers.
llvm-svn: 132136
2011-05-26 19:25:47 +00:00
Akira Hatanaka
5bfbea9ef2 Add support for C++ exception handling.
llvm-svn: 132131
2011-05-26 18:59:03 +00:00
Akira Hatanaka
5a8bd76f99 Set HasSetDirective to true.
llvm-svn: 132127
2011-05-26 18:16:18 +00:00
Akira Hatanaka
3f49cbeb37 Define WeakRefDirective.
llvm-svn: 132098
2011-05-25 23:30:30 +00:00
Akira Hatanaka
4806508364 Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
been defined in MipsInstrFPU.td.

llvm-svn: 132076
2011-05-25 20:08:05 +00:00
Akira Hatanaka
32b5043265 Custom-lower FCOPYSIGN nodes.
llvm-svn: 132074
2011-05-25 19:32:07 +00:00
Akira Hatanaka
ae2e2d557a Update MaxCallFrameSize regardless of the relocation model selected.
llvm-svn: 132070
2011-05-25 18:08:32 +00:00
Akira Hatanaka
953e0a3c45 Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should
return 0 if there are no function calls made. 

llvm-svn: 132065
2011-05-25 17:52:48 +00:00
Akira Hatanaka
33415b8179 Coding style fixes. Added comments.
llvm-svn: 132063
2011-05-25 17:32:06 +00:00