1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 21:42:54 +02:00
Commit Graph

81 Commits

Author SHA1 Message Date
Matt Arsenault
014e16538b R600/SI: Add intrinsic for ldexp
llvm-svn: 215734
2014-08-15 17:30:25 +00:00
Benjamin Kramer
da144ed5a2 Canonicalize header guards into a common format.
Add header guards to files that were missing guards. Remove #endif comments
as they don't seem common in LLVM (we can easily add them back if we decide
they're useful)

Changes made by clang-tidy with minor tweaks.

llvm-svn: 215558
2014-08-13 16:26:38 +00:00
Jan Vesely
c9798145af R600: Use optimized 24bit path in udivrem
v2: drop enum keyword
    use correct extension mode
    don't bother computing the sign in unsinged case

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 215462
2014-08-12 17:31:20 +00:00
Jan Vesely
a72063b855 R600: Remove unused code.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 215461
2014-08-12 17:31:19 +00:00
Jan Vesely
73bab311bb R600: Use i24 optimized path for SREM
v2: add tests
    rename LowerSDIV24 to LowerSDIVREM24
    handle the rem part in this function

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 215460
2014-08-12 17:31:17 +00:00
Matt Arsenault
d70c38a67b R600: Add new functions for splitting vector loads and stores.
These will be used in future patches and shouldn't change anything yet.

llvm-svn: 213877
2014-07-24 17:10:35 +00:00
Tom Stellard
ed0ccca70d R600/SI: Use scratch memory for large private arrays
llvm-svn: 213551
2014-07-21 15:45:01 +00:00
Tom Stellard
5bfbb25d6b R600/SI: Store constant initializer data in constant memory
This implements a solution for constant initializers suggested
by Vadim Girlin, where we store the data after the shader code
and then use the S_GETPC instruction to compute its address.

This saves use the trouble of creating a new buffer for constant data
and then having to pass the pointer to the kernel via user SGPRs or the
input buffer.

llvm-svn: 213530
2014-07-21 14:01:14 +00:00
Matt Arsenault
211ccabffb R600: Add dag combine for copy of an illegal type.
This helps avoid redundant instructions to unpack, and repack
the vectors. Ideally we could recognize that pattern and eliminate
it. Currently v4i8 and other small element type vectors are scalarized,
so this has the added bonus of avoiding that.

llvm-svn: 213031
2014-07-15 02:06:31 +00:00
Matt Arsenault
09212562b8 R600: Move mul combine to separate function
llvm-svn: 212052
2014-06-30 17:55:48 +00:00
Aaron Ballman
a5cd4afa00 Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended.
llvm-svn: 211783
2014-06-26 13:45:47 +00:00
Matt Arsenault
37d6d91b5b R600: Fix inconsistency in rsq instructions.
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

llvm-svn: 211637
2014-06-24 22:13:39 +00:00
Matt Arsenault
11e06d5cd5 R600: Remove DIV_INF
This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.

llvm-svn: 211616
2014-06-24 17:42:16 +00:00
Matt Arsenault
2fabae6272 R600: Remove AMDILISelLowering
llvm-svn: 211519
2014-06-23 18:00:55 +00:00
Jan Vesely
ce6de1b38d R600: Use LowerSDIVREM for i64 node replace
v2: move div/rem node replacement to R600ISelLowering
    make lowerSDIVREM protected

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211478
2014-06-22 21:43:01 +00:00
Jan Vesely
a58597d3d2 R600: Implement custom SDIVREM.
Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway.
SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient.

v2: Don't use all caps names

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211477
2014-06-22 21:43:00 +00:00
Matt Arsenault
b82983ef6a R600/SI: Add intrinsics for various math instructions.
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

llvm-svn: 211247
2014-06-19 01:19:19 +00:00
Matt Arsenault
c86884a54a R600: Handle fnearbyint
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.

llvm-svn: 211229
2014-06-18 22:03:45 +00:00
Matt Arsenault
a46ba4c9d1 R600/SI: Add intrinsics for brev instructions
llvm-svn: 211187
2014-06-18 17:13:57 +00:00
Matt Arsenault
068d030935 R600: Implement f64 ftrunc, ffloor and fceil.
CI has instructions for these, so this fixes them for older hardware.

llvm-svn: 211183
2014-06-18 17:05:30 +00:00
Matt Arsenault
77f7e6fc35 R600: Custom lower f64 frint for pre-CI
llvm-svn: 211182
2014-06-18 17:05:26 +00:00
Tom Stellard
a529beed9c R600: Use LDS and vectors for private memory
llvm-svn: 211110
2014-06-17 16:53:14 +00:00
Matt Arsenault
512b09be91 R600: Move / cleanup more leftover AMDIL stuff.
llvm-svn: 210998
2014-06-15 20:23:38 +00:00
Matt Arsenault
d4919ac014 R600: Move division custom lowering out of AMDILISelLowering
llvm-svn: 210997
2014-06-15 20:08:02 +00:00
Matt Arsenault
7c3e24fab1 R600: Remove dead code
llvm-svn: 210994
2014-06-15 19:48:13 +00:00
Matt Arsenault
e19ddbd0dc R600: Mostly remove remaining AMDIL intrinsics.
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
2014-06-12 21:15:44 +00:00
Matt Arsenault
a75d166beb R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
2014-06-11 17:50:44 +00:00
Matt Arsenault
6728d3c17d R600: Add helper functions.
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
2014-06-11 03:29:54 +00:00
Matt Arsenault
4ab9246e99 R600: Implement ComputeNumSignBitsForTargetNode for BFE
llvm-svn: 209460
2014-05-22 18:09:03 +00:00
Matt Arsenault
e43426533f R600: Add intrinsics for mad24
llvm-svn: 209456
2014-05-22 18:00:15 +00:00
Matt Arsenault
cb883e1e39 Remove unused method declaration
llvm-svn: 209174
2014-05-19 22:55:35 +00:00
Jay Foad
e0eac700cb Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
2014-05-14 21:14:37 +00:00
Tom Stellard
83d3208148 R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
llvm-svn: 208429
2014-05-09 16:42:16 +00:00
Craig Topper
9900b9f93b [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition
llvm-svn: 207503
2014-04-29 07:57:24 +00:00
Matt Arsenault
f022fe68e4 R600: Emit error instead of unreachable on function call
llvm-svn: 206904
2014-04-22 16:42:00 +00:00
Matt Arsenault
de91105f57 R600: Minor cleanups.
Fix indentation, better line wrapping, unused includes.

llvm-svn: 206562
2014-04-18 07:40:20 +00:00
Matt Arsenault
65fde80ac6 Move ExtractVectorElements to SelectionDAG.
This seems generally useful, and makes sense to
go along with SplitVector.

llvm-svn: 206041
2014-04-11 17:47:30 +00:00
Tom Stellard
557024a30d R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731
2014-04-07 19:45:41 +00:00
Matt Arsenault
a8674ddad8 R600: Add target nodes for BFM and BFI
llvm-svn: 205235
2014-03-31 18:21:13 +00:00
Matt Arsenault
7f99777a74 R600: Implement isZExtFree.
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

llvm-svn: 204946
2014-03-27 17:23:31 +00:00
Matt Arsenault
e42a0c31f3 R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
llvm-svn: 204945
2014-03-27 17:23:24 +00:00
Matt Arsenault
63960a4cd8 R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

llvm-svn: 204743
2014-03-25 18:18:27 +00:00
Matt Arsenault
7ae7f52221 R600: Implement isNarrowingProfitable.
llvm-svn: 204658
2014-03-24 19:43:31 +00:00
Matt Arsenault
553297669c R600: Match sign_extend_inreg to BFE instructions
llvm-svn: 204072
2014-03-17 18:58:11 +00:00
Craig Topper
b0056a4ca7 Switch all uses of LLVM_OVERRIDE to just use 'override' directly.
llvm-svn: 202621
2014-03-02 09:09:27 +00:00
Matt Arsenault
a3de4dc001 R600/SI - Add new CI arithmetic instructions.
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

llvm-svn: 202077
2014-02-24 21:01:28 +00:00
Benjamin Kramer
b51d0de00f R600: Always implement both versions of isTruncateFree and add a sanity check.
llvm-svn: 201222
2014-02-12 10:17:54 +00:00
Matt Arsenault
38609a2ae1 R600: Implement isTruncateFree
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

llvm-svn: 201107
2014-02-10 19:57:42 +00:00
Tom Stellard
d424fe57e4 R600: Add support for global addresses with constant initializers
llvm-svn: 199825
2014-01-22 19:24:21 +00:00
Tom Stellard
369c33de20 R600/SI: Add support for i8 and i16 private loads/stores
llvm-svn: 199823
2014-01-22 19:24:14 +00:00