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Author SHA1 Message Date
Quentin Colombet
191766f771 [X86][Haswell][SchedModel] Tidy up. 
<rdar://problem/15607571>

llvm-svn: 215924
 2014-08-18 17:56:01 +00:00
Quentin Colombet
35ae8395d0 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point XMM and YMM instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

llvm-svn: 215923
 2014-08-18 17:55:59 +00:00
Quentin Colombet
339e7a4ae7 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point XMM and YMM instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

llvm-svn: 215922
 2014-08-18 17:55:56 +00:00
Quentin Colombet
a553451324 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point XMM and YMM instructions.
Sub-group: Math instructions.

<rdar://problem/15607571>

llvm-svn: 215921
 2014-08-18 17:55:53 +00:00
Quentin Colombet
d6c4c7ce9b [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point XMM and YMM instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

llvm-svn: 215920
 2014-08-18 17:55:51 +00:00
Quentin Colombet
7c1df6f078 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point XMM and YMM instructions.
Sub-group: Conversion instructions.

<rdar://problem/15607571>

llvm-svn: 215919
 2014-08-18 17:55:49 +00:00
Quentin Colombet
f82b53ca5a [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point XMM and YMM instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

llvm-svn: 215918
 2014-08-18 17:55:46 +00:00
Quentin Colombet
2138e9d6a6 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer MMX and XMM instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

llvm-svn: 215917
 2014-08-18 17:55:43 +00:00
Quentin Colombet
5564e8d426 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer MMX and XMM instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

llvm-svn: 215916
 2014-08-18 17:55:41 +00:00
Quentin Colombet
1e0ae9ec68 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer MMX and XMM instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

llvm-svn: 215915
 2014-08-18 17:55:39 +00:00
Quentin Colombet
2e17eeecda [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer MMX and XMM instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

llvm-svn: 215914
 2014-08-18 17:55:36 +00:00
Quentin Colombet
5a5bf20c9d [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point x87 instructions.
Sub-group: Math instructions.

<rdar://problem/15607571>

llvm-svn: 215913
 2014-08-18 17:55:32 +00:00
Quentin Colombet
7cb8772661 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point x87 instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

llvm-svn: 215912
 2014-08-18 17:55:29 +00:00
Quentin Colombet
e9298615cc [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Floating Point x87 instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

llvm-svn: 215911
 2014-08-18 17:55:26 +00:00
Quentin Colombet
1f6b927d67 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

llvm-svn: 215910
 2014-08-18 17:55:23 +00:00
Quentin Colombet
18ca0e449b [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: Synchronization instructions.

<rdar://problem/15607571>

llvm-svn: 215909
 2014-08-18 17:55:21 +00:00
Quentin Colombet
cc1d8c9134 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: String instructions.

<rdar://problem/15607571>

llvm-svn: 215908
 2014-08-18 17:55:19 +00:00
Quentin Colombet
4256d926fe [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: Control transfer instructions.

<rdar://problem/15607571>

llvm-svn: 215907
 2014-08-18 17:55:16 +00:00
Quentin Colombet
ce7a0aea69 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

llvm-svn: 215906
 2014-08-18 17:55:13 +00:00
Quentin Colombet
05843ffc63 [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: Arithmetic instructions.

<rdar://problem/15607571>

llvm-svn: 215905
 2014-08-18 17:55:11 +00:00
Quentin Colombet
63d62b768f [X86][Haswell][SchedModel] Add architecture specific scheduling models. 
Group: Integer instructions.
Sub-group: Move instructions.

<rdar://problem/15607571>

llvm-svn: 215904
 2014-08-18 17:55:08 +00:00
Robin Morisset
92b539f285 Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends 
Summary:
Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends
These helper functions are introduced in D4844.
Depends D4844

Test Plan: make check-all passes

Reviewers: jfb

Subscribers: aemerson, llvm-commits, mcrosier, reames

Differential Revision: http://reviews.llvm.org/D4937

llvm-svn: 215902
 2014-08-18 16:48:58 +00:00
Aaron Ballman
5035042e58 Disabling an MSVC warning ('var' : definition from the for loop is ignored; the definition from the enclosing scope is used) which will trigger false positives more than true positives. 
llvm-svn: 215895
 2014-08-18 14:54:22 +00:00
Oliver Stannard
0f36700d69 Teach the AArch64 backend to handle f16 
This allows the AArch64 backend to handle fadd, fsub, fmul and fdiv
operations on f16 (half-precision) types by promoting to f32.

llvm-svn: 215891
 2014-08-18 14:22:39 +00:00
Oliver Stannard
159a549ea3 [ARM,AArch64] Do not tail-call to an externally-defined function with weak linkage 
Externally-defined functions with weak linkage should not be
tail-called on ARM or AArch64, as the AAELF spec requires normal calls
to undefined weak functions to be replaced with a NOP or jump to the
next instruction. The behaviour of branch instructions in this
situation (as used for tail calls) is implementation-defined, so we
cannot rely on the linker replacing the tail call with a return.

llvm-svn: 215890
 2014-08-18 12:42:15 +00:00
Elena Demikhovsky
e4fb4063fb AVX-512: Fixed a bug in emitting compare for MVT:i1 type. 
Added a test.

llvm-svn: 215889
 2014-08-18 11:59:06 +00:00
Aaron Ballman
da06e3f3de Silencing an MSVC warning about loop variable conflicting with a variable from an outer scope. NFC. 
llvm-svn: 215888
 2014-08-18 11:51:41 +00:00
Tim Northover
9127b613b1 TableGen: allow use of uint64_t for available features mask. 
ARM in particular is getting dangerously close to exceeding 32 bits worth of
possible subtarget features. When this happens, various parts of MC start to
fail inexplicably as masks get truncated to "unsigned".

Mostly just refactoring at present, and there's probably no way to test.

llvm-svn: 215887
 2014-08-18 11:49:42 +00:00
Abramo Bagnara
7d64c5c4b9 Added forgotten noexcept. 
llvm-svn: 215886
 2014-08-18 07:48:18 +00:00
Craig Topper
aa7422b5a6 Revert "Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid needing to mention the size." 
Getting a weird buildbot failure that I need to investigate.

llvm-svn: 215870
 2014-08-18 00:24:38 +00:00
Craig Topper
227456e133 Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid needing to mention the size. 
llvm-svn: 215868
 2014-08-17 23:47:00 +00:00
Rafael Espindola
619ce2fbb1 Use copy initialization to initialize std::unique_ptr. 
Thanks to David Blaikie for the suggestion.

llvm-svn: 215867
 2014-08-17 23:38:08 +00:00
Saleem Abdulrasool
d5ee75f890 ARM: mark missing functions from RTABI 
Simply indicate the functions that are part of the runtime library that we do
not setup libcalls for.  This is merely for ease of identification.  NFC.

llvm-svn: 215863
 2014-08-17 22:51:04 +00:00
Saleem Abdulrasool
dd9b2d6749 ARM: improve RTABI 4.2 conformance on Linux 
The set of functions defined in the RTABI was separated for no real reason.
This brings us closer to proper utilisation of the functions defined by the
RTABI.  It also sets the ground for correctly emitting function calls to AEABI
functions on all AEABI conforming platforms.

The previously existing lie on the behaviour of __ldivmod and __uldivmod is
propagated as it is beyond the scope of the change.

The changes to the test are due to the fact that we now use the divmod functions
which return both the quotient and remainder and thus we no longer need to
invoke two functions on Linux (making it closer to EABI's behaviour).

llvm-svn: 215862
 2014-08-17 22:51:02 +00:00
Saleem Abdulrasool
bead350432 ARM: whitespace 
Whitespace fix, NFC.

llvm-svn: 215861
 2014-08-17 22:50:59 +00:00
Rafael Espindola
18a47f1b82 Remove unused member variable. 
llvm-svn: 215860
 2014-08-17 22:48:55 +00:00
Rafael Espindola
4dd4e8c9ed Return a std::uinque_ptr. Every caller was already using one. 
llvm-svn: 215858
 2014-08-17 22:37:39 +00:00
Rafael Espindola
0f0b067a94 Convert an ownership comment with std::uinque_ptr. 
llvm-svn: 215855
 2014-08-17 22:20:33 +00:00
Rafael Espindola
164d599b63 Pass a std::uinque_ptr to ParseAssembly to make the ownership explicit. NFC. 
llvm-svn: 215852
 2014-08-17 21:36:47 +00:00
Rafael Espindola
23e76772b0 getLazyIRModule always takes ownership. Make that explicit. 
llvm-svn: 215851
 2014-08-17 21:22:19 +00:00
Rafael Espindola
b75d8cc14e Return a std::unique_ptr to make the ownership explicit. 
llvm-svn: 215850
 2014-08-17 21:11:31 +00:00
Rafael Espindola
3e9ce8a1ac Don't repeat the function name in comments. NFC. 
llvm-svn: 215849
 2014-08-17 21:05:08 +00:00
Rafael Espindola
490e26c356 Don't repeat names in comments. NFC. 
llvm-svn: 215848
 2014-08-17 20:57:50 +00:00
Daniel Sanders
85d824c210 Revert: r215698 - Current implementation of c.cond.fmt instructions only accept default cc0 register... 
It causes a number of regressions when -fintegrated-as is enabled. This happens
because there are codegen-only instructions that incorrectly uses the first
operand as the encoding for the $fcc register. The regressions do not occur when
-via-file-asm is also given.

llvm-svn: 215847
 2014-08-17 19:47:47 +00:00
Saleem Abdulrasool
5df0772d37 ARM: correct toggling behaviour 
This was a thinko.  The intent was to flip the explicit bits that need toggling
rather than all bits.  This would result in incorrect behaviour (which now is
tested).

Thanks to Nico Weber for pointing this out!

llvm-svn: 215846
 2014-08-17 19:20:38 +00:00
Rafael Espindola
cb64eee66e llvm-objdump: don't print relocations in non-relocatable files. 
This matches the behavior of GNU objdump.

llvm-svn: 215844
 2014-08-17 19:09:37 +00:00
Rafael Espindola
6acfd7d2c4 Remove a redundant "public:". NFC. 
llvm-svn: 215842
 2014-08-17 18:33:17 +00:00
Hans Wennborg
5a2722e909 BumpPtrAllocator: remove 'no slabs allocated yet' check 
We already handle the no-slabs case when checking whether the current slab
is large enough: if no slabs have been allocated, CurPtr and End are both 0.
alignPtr(0), will still be 0, and so "if (Ptr + Size <= End)" fails.

Differential Revision: http://reviews.llvm.org/D4943

llvm-svn: 215841
 2014-08-17 18:31:18 +00:00
Rafael Espindola
b81f06cd2c Add a non-templated ELFObjectFileBase class. 
Use it to implement some ELF only virtual interfaces instead of using error
prone series of dyn_casts.

llvm-svn: 215838
 2014-08-17 17:52:10 +00:00
Rafael Espindola
c4b48a6a79 Fix an off-by-one bug in the target independent llvm-objdump. 
It would prevent the display of a single byte instruction before a label.

Patch by Steve King!

llvm-svn: 215837
 2014-08-17 16:31:39 +00:00