1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00

131999 Commits

Author SHA1 Message Date
Simon Pilgrim
1da08bcea1 [X86][SSE2] Fixed shuffle of results in _mm_cmpnge_sd/_mm_cmpngt_sd tests
llvm-svn: 270080
2016-05-19 16:49:53 +00:00
Mitch Bodart
c83bd382db CodeGen: Move check of EnablePostRAScheduler to avoid disabling antidependency breaker
Previously, specifying -post-RA-scheduler=true had the side effect of
disabling the antidependency breaker, yielding different behavior than
if the post-RA-scheduler was enabled via the scheduling model.

Differential Revision: http://reviews.llvm.org/D20186

llvm-svn: 270077
2016-05-19 16:40:49 +00:00
George Rimar
bcbd39476b Temporarily revert r270070
It broke buildbot:
http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/4817/steps/ninja%20check%201/logs/stdio

Actually it is just because D20273 not yet commited, but these 2 were crossing with each other,
and I`ll better find the way to land them separatelly soon.

Initial commit message:

[llvm-mc] - Teach llvm-mc to generate compressed debug sections in zlib style.

Before this patch llvm-mc generated zlib-gnu styled sections. 
That means no SHF_COMPRESSED flag was set, magic 'zlib' signature
was used in combination with full size field. Sections were renamed to "*.z*".
This patch reimplements the compression style to zlib one as zlib-gnu looks
to be depricated everywhere.

Differential revision: http://reviews.llvm.org/D20331

llvm-svn: 270075
2016-05-19 15:58:05 +00:00
Davide Italiano
31f2c5f8e5 [SCCP] Prefer class to struct.
llvm-svn: 270074
2016-05-19 15:58:02 +00:00
Sanjay Patel
0aebfa9d81 [SelectionDAG] rename/move isKnownToBeAPowerOfTwo() from TargetLowering (NFC)
There are at least 2 places (DAGCombiner, X86ISelLowering) where this could be used instead
of ad-hoc and watered down code that is trying to match a power-of-2 pattern.

Differential Revision: http://reviews.llvm.org/D20439

llvm-svn: 270073
2016-05-19 15:53:52 +00:00
Matthew Simpson
1384b0c2ff [LAA] Check independence of strided accesses before forward case
This patch changes the order in which we attempt to prove the independence of
strided accesses. We previously did this after we knew the dependence distance
was positive. With this change, we check for independence before handling the
negative distance case. The patch prevents LAA from reporting forward
dependences for independent strided accesses.

This change was requested in the review of D19984.

llvm-svn: 270072
2016-05-19 15:37:19 +00:00
George Rimar
b073169892 [llvm-mc] - Teach llvm-mc to generate compressed debug sections in zlib style.
Before this patch llvm-mc generated zlib-gnu styled sections. 
That means no SHF_COMPRESSED flag was set, magic 'zlib' signature
was used in combination with full size field. Sections were renamed to "*.z*".
This patch reimplements the compression style to zlib one as zlib-gnu looks
to be depricated everywhere.

Differential revision: http://reviews.llvm.org/D20331

llvm-svn: 270070
2016-05-19 15:08:31 +00:00
Chad Rosier
d705b5562f [AArch64 ] Generate a BFXIL from 'or (and X, Mask0Imm),(and Y, Mask1Imm)'.
Mask0Imm and ~Mask1Imm must be equivalent and one of the MaskImms is a shifted
mask (e.g., 0x000ffff0).  Both 'and's must have a single use.

This changes code like:

  and w8, w0, #0xffff000f
  and w9, w1, #0x0000fff0
  orr w0, w9, w8

into

  lsr w8, w1, #4
  bfi w0, w8, #4, #12

llvm-svn: 270063
2016-05-19 14:19:47 +00:00
Ranjeet Singh
5c670ba3e8 [ARM] Add cdp intrinsic tests.
- Renamed intrinsics.ll to intrinsics-coprocessor.ll
  as all the tests were testing coprocessor instructions,
  also made the test checks match the full instruction.

Differential Revision: http://reviews.llvm.org/D20393

llvm-svn: 270057
2016-05-19 12:59:17 +00:00
Ranjeet Singh
7f495daec3 Test commit.
llvm-svn: 270056
2016-05-19 12:44:39 +00:00
Artem Tamazov
eea90f5cc7 [AMDGPU][llvm-mc] Fixes to support buffer atomics.
Fixes for MUBUF_Atomic instructions to make operand list valid:
 - For RTN insns, make a copy of $vdata_in operand as $vdata.
 - Do not add operand for GLC, it is hardcoded and comes as a token.
Workaround to avoid adding multiple default optional operands.
Tests added.

Differential Revision: http://reviews.llvm.org/D20257

llvm-svn: 270049
2016-05-19 12:22:39 +00:00
Zoran Jovanovic
07314a2bff ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocation
Differential Revision: http://reviews.llvm.org/D15526

llvm-svn: 270048
2016-05-19 12:20:40 +00:00
Simon Pilgrim
52b8aeda48 [X86][SSE2] Added _mm_move_* tests
llvm-svn: 270046
2016-05-19 11:59:57 +00:00
Simon Pilgrim
7db2a58619 [X86][SSE2] Added _mm_cast* and _mm_set* tests
llvm-svn: 270041
2016-05-19 10:58:54 +00:00
Daniel Sanders
7b472cd465 [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.
Summary: Partially fixes PR27458

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20330

llvm-svn: 270037
2016-05-19 10:42:14 +00:00
Andrey Turetskiy
ccc62bdbb9 [X86] Enable RRL part of the LEA optimization pass for -O2.
Enable "Remove Redundant LEAs" part of the LEA optimization pass for -O2.
This gives 6.4% performance improve on Broadwell on nnet benchmark from Coremark-pro.
There is no significant effect on other benchmarks (Geekbench, Spec2000, Spec2006).

Differential Revision: http://reviews.llvm.org/D19659

llvm-svn: 270036
2016-05-19 10:18:29 +00:00
Zlatko Buljan
3d28e4b8d5 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
2016-05-19 07:31:28 +00:00
Craig Topper
1aff453749 [X86] Generalize and combine some similar type constraints and node types. No changes to the isel table size so the separation wasn't buying us anything.
llvm-svn: 270026
2016-05-19 06:13:58 +00:00
Craig Topper
c298b9dab5 [X86] Simplify some type constraints by removing parts that were already implied.
llvm-svn: 270025
2016-05-19 06:13:48 +00:00
Peter Collingbourne
1d69c09bab CodeGen: Make the global-merge pass independently testable, and add a test.
llvm-svn: 270023
2016-05-19 04:38:56 +00:00
Vedant Kumar
d34b10ac08 Retry^3 "[ProfileData] (llvm) Use Error in InstrProf and Coverage, NFC"
Transition InstrProf and Coverage over to the stricter Error/Expected
interface.

Changes since the initial commit:
- Fix error message printing in llvm-profdata.
- Check errors in loadTestingFormat() + annotateAllFunctions().
- Defer error handling in InstrProfIterator to InstrProfReader.
- Remove the base ProfError class to work around an MSVC ICE.

Differential Revision: http://reviews.llvm.org/D19901

llvm-svn: 270020
2016-05-19 03:54:45 +00:00
Sanjoy Das
b590ade35e [GuardWidening] Use getEquivalentICmp to fold constant compares
`ConstantRange::getEquivalentICmp` is more general, and better
factored.

llvm-svn: 270019
2016-05-19 03:53:17 +00:00
Sanjoy Das
c63bcd9d33 [ConstantRange] Add an getEquivalentICmp helper
Currently only its unit test uses it, but this will be used in a later
change to simplify some logic in the GuardWidening pass.

llvm-svn: 270018
2016-05-19 03:53:06 +00:00
Dan Gohman
bb2c8e5fad [WebAssembly] Update WebAssembly target for r269988.
llvm-svn: 270017
2016-05-19 03:00:05 +00:00
Craig Topper
4a761c4c76 [X86] Remove some type constraint classes and use already existing stricter classes.
llvm-svn: 270013
2016-05-19 02:05:58 +00:00
Craig Topper
f553944514 [AVX512] Strengthen type constraints for VFIXUPIMM patterns and combine the type constraints for vector and scalar.
llvm-svn: 270012
2016-05-19 02:05:55 +00:00
Dan Gohman
65295f5464 [WebAssembly] Make several CHECK lines less fragile using regexes and CHECK-DAG.
llvm-svn: 270011
2016-05-19 01:52:56 +00:00
Eugene Zelenko
7ecab2b09a Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings in examples; other minor fixes.
Differential revision: http://reviews.llvm.org/D20397

llvm-svn: 270008
2016-05-19 01:08:04 +00:00
Sanjay Patel
8833a2ff67 reduce indentation; NFCI
llvm-svn: 270007
2016-05-19 00:33:07 +00:00
Chad Rosier
889772f9e3 [AArch64] Push comment into function. NFC.
llvm-svn: 270003
2016-05-18 23:51:17 +00:00
Matt Arsenault
6728e29c35 AMDGPU: Fix verifier error when spilling undef subreg
llvm-svn: 270002
2016-05-18 23:35:53 +00:00
Chris Bieneman
fa3ade1f8d [obj2yaml] Refactoring of dumping MachO section structs
This refactoring is to reduce code duplication between the 32-bit and 64-bit code paths. This refactoring will also make the special casing for other data after load commands cleaner.

llvm-svn: 270001
2016-05-18 23:22:53 +00:00
Matt Arsenault
efc0ca4c19 AMDGPU: Fix promote alloca for pointer loads
If the load has a pointer type, we don't want to change
its type.

llvm-svn: 270000
2016-05-18 23:20:24 +00:00
Sanjoy Das
cbd9afc190 [LowerGuards] Rename variable; NFC
PredicatePassProbability is a better name for what LikelyBranchWeight
was trying to express.

llvm-svn: 269999
2016-05-18 23:16:27 +00:00
Sanjoy Das
479a57ca4a New pass: guard widening
Summary:
Implement guard widening in LLVM. Description from GuardWidening.cpp:

The semantics of the `@llvm.experimental.guard` intrinsic lets LLVM
transform it so that it fails more often that it did before the
transform.  This optimization is called "widening" and can be used hoist
and common runtime checks in situations like these:

```
%cmp0 = 7 u< Length
call @llvm.experimental.guard(i1 %cmp0) [ "deopt"(...) ]
call @unknown_side_effects()
%cmp1 = 9 u< Length
call @llvm.experimental.guard(i1 %cmp1) [ "deopt"(...) ]
...
```

to

```
%cmp0 = 9 u< Length
call @llvm.experimental.guard(i1 %cmp0) [ "deopt"(...) ]
call @unknown_side_effects()
...
```

If `%cmp0` is false, `@llvm.experimental.guard` will "deoptimize" back
to a generic implementation of the same function, which will have the
correct semantics from that point onward.  It is always _legal_ to
deoptimize (so replacing `%cmp0` with false is "correct"), though it may
not always be profitable to do so.

NB! This pass is a work in progress.  It hasn't been tuned to be
"production ready" yet.  It is known to have quadriatic running time and
will not scale to large numbers of guards

Reviewers: reames, atrick, bogner, apilipenko, nlewycky

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D20143

llvm-svn: 269997
2016-05-18 22:55:34 +00:00
Dehao Chen
7cac814db8 Follow-up patch of http://reviews.llvm.org/D19948 to handle missing profiles when simplifying CFG.
Summary: Set default branch weight to 1:1 if one of the branch has profile missing when simplifying CFG.

Reviewers: spatel, davidxl

Subscribers: danielcdh, llvm-commits

Differential Revision: http://reviews.llvm.org/D20307

llvm-svn: 269995
2016-05-18 22:41:03 +00:00
Haicheng Wu
93eb34a12b [MBP] Remove a redundant skipFunction(). NFC.
skipFunction() is called twice.

Differential Revision: http://reviews.llvm.org/D20377

llvm-svn: 269994
2016-05-18 22:34:45 +00:00
Richard Smith
b9f1b721c1 Work around a glibc bug: backtrace() spuriously fails if
- glibc is dynamically linked, and
 - libgcc_s is unavailable (for instance, another library is being used to
   provide the compiler runtime or libgcc is statically linked), and
 - the target is x86_64.

If we run backtrace() and it fails to find any stack frames, try using
_Unwind_Backtrace instead if available.

llvm-svn: 269992
2016-05-18 22:26:36 +00:00
Sanjay Patel
428d853c02 fix formatting; NFC
llvm-svn: 269990
2016-05-18 22:05:28 +00:00
Rafael Espindola
22e87bbb08 Delete Reloc::Default.
Having an enum member named Default is quite confusing: Is it distinct
from the others?

This patch removes that member and instead uses Optional<Reloc> in
places where we have a user input that still hasn't been maped to the
default value, which is now clear has no be one of the remaining 3
options.

llvm-svn: 269988
2016-05-18 22:04:49 +00:00
Jacques Pienaar
30194757f7 [lanai] Change the way flag setting instructions are checked.
isReturn() was returning different values with and without -g which led to
different code being generated. Change isFlagSettingInstruction to query
an instruction's effect on SR instead.

llvm-svn: 269986
2016-05-18 21:31:37 +00:00
Michael Zolotukhin
60d4945387 [LoopUnrollAnalyzer] Take into account cost of instructions controlling branches, along with their operands.
Previously, we didn't add their and their operands cost, which could've
resulted in unrolling loops for no actual benefit.

llvm-svn: 269985
2016-05-18 21:20:12 +00:00
Sanjay Patel
44b7177a90 [x86] add test for immediate comment formatting
llvm-svn: 269977
2016-05-18 20:26:32 +00:00
Dan Gohman
2ff0f2e766 [WebAssembly] Disable the MachineScheduler.
llvm-svn: 269976
2016-05-18 20:19:02 +00:00
Chris Bieneman
3d2fca5d0f Fixing test failure on Windows bot
http://bb.pgr.jp/builders/msbuild-llvmclang-x64-msc19-DA/builds/553/steps/test-llvm/logs/LLVM%20%3A%3A%20ObjectYAML__MachO__load_commands.yaml

llvm-svn: 269975
2016-05-18 20:01:48 +00:00
Dehao Chen
d2915158e8 clang-format SimplifyCFG.cpp.
llvm-svn: 269974
2016-05-18 19:44:21 +00:00
Jan Vesely
0f6b39e33f AMDGPU: Fix incorrect simm check
Use signed division otherwise all back jumps fail the check
Fixes regression introduced in r269951

Differential Revision: http://reviews.llvm.org/D20380

llvm-svn: 269972
2016-05-18 19:07:58 +00:00
Krzysztof Parzyszek
72f4c82ed6 When looking for a spill slot in reg scavenger, find one that matches RC
When looking for an available spill slot, the register scavenger would stop
after finding the first one with no register assigned to it. That slot may
have size and alignment that do not meet the requirements of the register
that is to be spilled. Instead, find an available slot that is the closest
in size and alignment to one that is needed to spill a register from RC.

Differential Revision: http://reviews.llvm.org/D20295

llvm-svn: 269969
2016-05-18 18:16:00 +00:00
Simon Pilgrim
06fff37e6e [X86][SSE2] Added fast-isel tests to sync with clang/test/CodeGen/sse2-builtins.c
llvm-svn: 269966
2016-05-18 18:00:43 +00:00
Chad Rosier
4ef3f73429 [AArch64] Minor refactoring. NFC.
llvm-svn: 269963
2016-05-18 17:43:11 +00:00