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Commit Graph

3113 Commits

Author SHA1 Message Date
Devang Patel
1da8253b35 Removoe MachineModuleInfo methods (and related DebugInfoDesc class hierarchy) that were used to handle debug info.
llvm-svn: 62199
2009-01-13 23:54:55 +00:00
Devang Patel
7a618394f6 Undo previous checkin.
llvm-svn: 62190
2009-01-13 22:54:57 +00:00
Devang Patel
ab5ef6abf1 Use dwarf writer to decide whether the module has debug info or not.
llvm-svn: 62184
2009-01-13 21:25:00 +00:00
Dan Gohman
9e9858781c The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

llvm-svn: 62177
2009-01-13 20:24:13 +00:00
Duncan Sands
975f2428ba When replacing uses and the same node is reached
via two paths, process it once not twice, d'oh!
Analysis, testcase and original patch thanks to
Mon Ping Wang.

llvm-svn: 62169
2009-01-13 15:17:14 +00:00
Duncan Sands
439d97a6cb Fix some typos. Also, the WidenedVectors map
was not being cleaned by ExpungeNode.

llvm-svn: 62167
2009-01-13 14:42:39 +00:00
Duncan Sands
8267463dec Correct a comment - this is not a sign extension.
llvm-svn: 62166
2009-01-13 14:04:14 +00:00
Devang Patel
eed0505ed8 Use DebugInfo interface to lower dbg_* intrinsics.
llvm-svn: 62127
2009-01-13 00:35:13 +00:00
Duncan Sands
bcdbfb63dc Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.

llvm-svn: 62099
2009-01-12 20:38:59 +00:00
Evan Cheng
5e17ea36e1 Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency.
Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet.

llvm-svn: 62074
2009-01-12 03:19:55 +00:00
Evan Cheng
e280fcfbbc CheckForPhysRegDependency should not return copy cost. It's not used. No functionality change.
llvm-svn: 62036
2009-01-11 08:53:35 +00:00
Evan Cheng
411c48b7d2 Duplicated node may produce a non-physical register def.
llvm-svn: 62015
2009-01-09 22:44:02 +00:00
Evan Cheng
7a918ea197 Minor debug output tweak.
llvm-svn: 62005
2009-01-09 20:42:34 +00:00
Devang Patel
7fd7643d23 Request DwarfWriter. This will be used to handle dbg_* intrinsics.
llvm-svn: 61999
2009-01-09 19:11:50 +00:00
Misha Brukman
71c7e40966 Removed trailing whitespace from Makefiles.
llvm-svn: 61991
2009-01-09 16:44:42 +00:00
Dan Gohman
3579548f68 Remove redundant 'else's. No functionality change.
llvm-svn: 61891
2009-01-07 22:30:55 +00:00
Dan Gohman
b19f5073f9 Fix a bug in ComputeLinearIndex computation handling multi-level
aggregate types. Don't increment the current index after reaching
the end of a struct, as it will already be pointing at
one-past-the end. This fixes PR3288.

llvm-svn: 61828
2009-01-06 22:53:52 +00:00
Dan Gohman
595c38acb0 Update these argument lists for the isNormalMemory
argument. This doesn't affect current functionality.

llvm-svn: 61779
2009-01-06 01:28:56 +00:00
Dan Gohman
1cdb677fc8 Use a latency value of 0 for the artificial edges inserted by
AddPseudoTwoAddrDeps. This lets the scheduling infrastructure
avoid recalculating node heights. In very large testcases this
was a major bottleneck. Thanks to Roman Levenstein for finding
this!

As a side effect, fold-pcmpeqd-0.ll is now scheduled better
and it no longer requires spilling on x86-32.

llvm-svn: 61778
2009-01-06 01:19:04 +00:00
Dan Gohman
9938898e44 TargetLowering.h #includes SelectionDAGNodes.h, so it doesn't need its
own OpActionsCapacity magic number; it can just use ISD::BUILTIN_OP_END,
as long as it takes care to round up when needed.

llvm-svn: 61733
2009-01-05 19:40:39 +00:00
Dan Gohman
8271066844 Tidy up #includes, deleting a bunch of unnecessary #includes.
llvm-svn: 61715
2009-01-05 17:59:02 +00:00
Devang Patel
689e130117 squash warnings.
llvm-svn: 61707
2009-01-05 17:31:22 +00:00
Dan Gohman
2a079de3f5 Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.
llvm-svn: 61613
2009-01-03 19:22:06 +00:00
Dan Gohman
8dc1513b6c CommuteNodesToReducePressure() is now removed.
llvm-svn: 61612
2009-01-03 19:19:30 +00:00
Dan Gohman
6a518de5f5 Remove the code from the scheduler that commuted two-address
instructions to avoid copies, because TwoAddressInstructionPass
also does this optimization.  The scheduler's version didn't
account for live-out values, which resulted in spurious commutes
and missed opportunities.

Now, TwoAddressInstructionPass handles all the opportunities,
instead of just those that the scheduler missed. The result is
usually the same, though there are occasional trivial differences
resulting from the avoidance of spurious commutes.

llvm-svn: 61611
2009-01-03 18:01:46 +00:00
Duncan Sands
0fca32114b Factorize (and generalize) the code promoting SELECT
and BRCOND conditions.  Reorder a few methods while
there.

llvm-svn: 61547
2009-01-01 20:36:20 +00:00
Duncan Sands
07002edaca Remove trailing spaces.
llvm-svn: 61545
2009-01-01 19:56:02 +00:00
Duncan Sands
190d6bc636 Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).

llvm-svn: 61542
2009-01-01 15:52:00 +00:00
Scott Michel
5bb7db3872 Teach LeaglizeDAG that i64 mul can be a libcall.
llvm-svn: 61463
2008-12-29 03:21:37 +00:00
Dale Johannesen
88e47fa0e4 Change comments so everybody can understand them, hopefully.
llvm-svn: 61405
2008-12-23 23:47:22 +00:00
Dale Johannesen
e1a3d2da49 Add another permutation where we should get rid of a-a.
llvm-svn: 61401
2008-12-23 23:01:27 +00:00
Anton Korobeynikov
328347152a Restore debug printing
llvm-svn: 61398
2008-12-23 22:26:18 +00:00
Anton Korobeynikov
f4a9c57b23 Sometimes APInt syntax is really ugly... :(
llvm-svn: 61397
2008-12-23 22:26:01 +00:00
Anton Korobeynikov
a2055f8f17 Indent stuff properly
llvm-svn: 61396
2008-12-23 22:25:45 +00:00
Anton Korobeynikov
9559c8c377 Initial checkin of APInt'ififcation of switch lowering
llvm-svn: 61395
2008-12-23 22:25:27 +00:00
Dan Gohman
a0f1fc06c4 Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.

llvm-svn: 61389
2008-12-23 21:37:04 +00:00
Dan Gohman
6bee7ef264 Rename BuildSchedUnits to BuildSchedGraph, and refactor the
code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions.

llvm-svn: 61376
2008-12-23 18:36:58 +00:00
Dan Gohman
b4060b4995 Avoid an unnecessary call to allnodes_size(), which is linear.
llvm-svn: 61372
2008-12-23 17:24:50 +00:00
Dale Johannesen
425b44516f One more permutation of subtracting off a base value.
llvm-svn: 61361
2008-12-23 01:59:54 +00:00
Mon P Wang
84ad2a383d Added support for vector widening.
llvm-svn: 61209
2008-12-18 20:03:17 +00:00
Mon P Wang
bc3622287b Fix expansion of vsetcc to set the high bit for true instead of 1.
llvm-svn: 61129
2008-12-17 08:49:47 +00:00
Dan Gohman
a8796f4908 Double the amount of memory reserved for SUnits. This is a
temporary workaround for an obscure bug. When node cloning is
used, it is possible that more SUnits will be created, and
if the SUnits std::vector has to reallocate, it will
invalidate all the graph edges.

llvm-svn: 61122
2008-12-17 04:30:46 +00:00
Eli Friedman
4aae828bf8 Fix for PR3225: disable a broken optimization in
DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

In terms of restoring the optimization, the best fix here isn't 
obvious... any ideas?

llvm-svn: 61119
2008-12-17 03:35:17 +00:00
Dale Johannesen
e348900657 A new dag combine; several permutations of this
are there under ADD, this one was missing.

llvm-svn: 61107
2008-12-16 22:13:49 +00:00
Dan Gohman
f8f5625748 Preserve SourceValue information when lowering produces multiple loads from
different offsets within the same stack slot.

llvm-svn: 61093
2008-12-16 18:25:36 +00:00
Evan Cheng
96d87db03b We have decided not to support inline asm where an output operand with a matching input operand with incompatible type (i.e. either one is a floating point and the other is an integer or the sizes of the types differ). SelectionDAGBuild will catch these and exit with an error.
llvm-svn: 61092
2008-12-16 18:21:39 +00:00
Dan Gohman
e2cf452271 Remove some special-case logic in ScheduleDAGSDNodes's
latency computation code that is no longer needed with the
new method for handling latencies.

llvm-svn: 61074
2008-12-16 03:31:11 +00:00
Dan Gohman
40a40dd7c1 Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.

Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.

Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.

llvm-svn: 61073
2008-12-16 03:25:46 +00:00
Dan Gohman
23aae3bba9 Make addPred and removePred return void, since the return value is not
currently used by anything.

llvm-svn: 61066
2008-12-16 01:00:55 +00:00
Mon P Wang
bb3c2994f0 Added support for splitting and scalarizing vector shifts.
llvm-svn: 61050
2008-12-15 21:44:00 +00:00