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80 Commits

Author SHA1 Message Date
Vladimir Medic
e3aeddca47 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
llvm-svn: 186397
 2013-07-16 10:07:14 +00:00
Vladimir Medic
8e12e22a4d Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 186151
 2013-07-12 09:25:35 +00:00
Vladimir Medic
d4a8ab4928 Reverting commit r185999 due to buildboot failure. 
llvm-svn: 186000
 2013-07-10 12:26:26 +00:00
Vladimir Medic
408af148a4 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 185999
 2013-07-10 10:18:10 +00:00
Akira Hatanaka
96de87d87c [mips] Trap on integer division by zero. 
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
 2013-05-20 18:07:43 +00:00
Akira Hatanaka
587ba11650 [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180241
 2013-04-25 01:21:25 +00:00
Akira Hatanaka
fd15a7b67e [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180238
 2013-04-25 01:11:15 +00:00
Akira Hatanaka
0a152f4724 [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
 2013-04-19 19:03:11 +00:00
Akira Hatanaka
a989d1f25d [mips] Add definition of JALR instruction which has two register operands. Change the 
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
 2013-02-07 19:48:00 +00:00
Akira Hatanaka
9a19eb22dc [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0". 
llvm-svn: 174546
 2013-02-06 21:50:15 +00:00
Akira Hatanaka
7477b1b91f [mips] 80 columns. 
llvm-svn: 171515
 2013-01-04 19:38:05 +00:00
Akira Hatanaka
d01b04ad93 [mips] Refactor instructions which move data from or to coprocessors. 
llvm-svn: 171510
 2013-01-04 19:13:49 +00:00
Akira Hatanaka
6d30f89eeb [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.

llvm-svn: 170956
 2012-12-21 23:21:32 +00:00
Akira Hatanaka
b41ed048b6 [mips] Refactor SYNC and multiply/divide instructions. 
llvm-svn: 170955
 2012-12-21 23:17:36 +00:00
Akira Hatanaka
6b9b8a5489 [mips] Refactor BAL instructions. 
llvm-svn: 170954
 2012-12-21 23:15:59 +00:00
Akira Hatanaka
abfa7cf8bf [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
llvm-svn: 170952
 2012-12-21 23:03:50 +00:00
Akira Hatanaka
607c79d3a2 [mips] Refactor LUI instruction. 
llvm-svn: 170944
 2012-12-21 22:46:07 +00:00
Akira Hatanaka
5953571624 [mips] Refactor count leading zero or one instructions. 
llvm-svn: 170942
 2012-12-21 22:43:58 +00:00
Akira Hatanaka
aae0730c16 [mips] Refactor sign-extension-in-register instructions. 
llvm-svn: 170940
 2012-12-21 22:41:52 +00:00
Akira Hatanaka
28f3fe9725 [mips] Refactor instructions which copy from and to HI/LO registers. 
llvm-svn: 170939
 2012-12-21 22:39:17 +00:00
Akira Hatanaka
e0e871529a [mips] Refactor SLT (set on less than) instructions. Separate encoding 
information from the rest. 

llvm-svn: 170664
 2012-12-20 04:27:52 +00:00
Akira Hatanaka
0c5b53d93f [mips] Refactor unconditional branch instruction. Separate encoding information 
from the rest. 

llvm-svn: 170663
 2012-12-20 04:22:39 +00:00
Akira Hatanaka
9ed2d54e79 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka
3266206836 [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.

llvm-svn: 170659
 2012-12-20 04:13:23 +00:00
Akira Hatanaka
654c74a52d [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.

llvm-svn: 170657
 2012-12-20 04:10:13 +00:00
Akira Hatanaka
06f2007a02 [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.

llvm-svn: 170650
 2012-12-20 03:48:24 +00:00
Akira Hatanaka
c627c88fc5 [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.

llvm-svn: 170649
 2012-12-20 03:44:41 +00:00
Akira Hatanaka
689a2c61b4 [mips] Refactor arithmetic and logic instructions with immediate operands. 
Separate encoding information from the rest.

llvm-svn: 170648
 2012-12-20 03:40:03 +00:00
Akira Hatanaka
78d41e6181 [mips] Refactor arithmetic and logic instructions. Separate encoding 
information from the rest.

llvm-svn: 170647
 2012-12-20 03:34:05 +00:00
Akira Hatanaka
9b0bb584d7 [mips] Delete all floating point instruction classes that are no longer used. 
No functionality change.

llvm-svn: 170084
 2012-12-13 02:05:02 +00:00
Akira Hatanaka
8a20e0e5f7 [mips] Modify definitions of floating point conditional move instructions. 
No functionality change.

llvm-svn: 170080
 2012-12-13 01:41:15 +00:00
Akira Hatanaka
91fcd99fe7 [mips] Modify definitions of floating point comparison instructions. 
No functionality change.

llvm-svn: 170077
 2012-12-13 01:34:09 +00:00
Akira Hatanaka
a2c716142c [mips] Modify definitions of floating point branch instructions. 
No functionality change.

llvm-svn: 170076
 2012-12-13 01:32:36 +00:00
Akira Hatanaka
1adf30b9d9 [mips] Modify definitions of floating point indexed load and store instructions. 
No functionality change.

llvm-svn: 170075
 2012-12-13 01:30:49 +00:00
Akira Hatanaka
98db320b09 [mips] Modify definitions of floating point multiply-add/sub instructions. 
No functionality change.

llvm-svn: 170073
 2012-12-13 01:27:48 +00:00
Akira Hatanaka
c9ffc6e2aa [mips] Modify definitions of floating point load and store instructions. 
No functionality change.

llvm-svn: 170072
 2012-12-13 01:24:00 +00:00
Akira Hatanaka
8870233371 [mips] Modify definitions of move from/to coprocessor instructions. 
No functionality change.

llvm-svn: 170071
 2012-12-13 01:16:49 +00:00
Akira Hatanaka
ec241a272b [mips] Modify definitions of two register operand floating point instructions. 
No functionality change.

llvm-svn: 170069
 2012-12-13 01:14:07 +00:00
Akira Hatanaka
3e348c6459 [mips] Modify definitions of three register operand floating point instructions 
and separate encoding information from the rest.

llvm-svn: 170066
 2012-12-13 01:07:37 +00:00
Akira Hatanaka
5b3f83b790 [mips] Move classes that do not belong in MipsInstrFormats.td into 
MipsInstrFPU.td.
 

llvm-svn: 170061
 2012-12-13 00:49:23 +00:00
Akira Hatanaka
09dbe69401 [mips] Remove single-precision floating point instruction from multiclass 
FFR2P_M.
 

llvm-svn: 170055
 2012-12-13 00:35:54 +00:00
Akira Hatanaka
27204fd141 [mips] Remove single-precision floating point instructions from multiclasses 
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053
 2012-12-13 00:29:29 +00:00
Akira Hatanaka
57161323ed [mips] Shorten predicate name. 
llvm-svn: 169579
 2012-12-07 03:06:09 +00:00
Jack Carter
c5f946b170 Adding support for instructions mfc0, mfc2, mtc0, mtc2 
move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351
 2012-10-06 01:17:37 +00:00
Jack Carter
a6d222bf00 Implement methods that enable expansion of load immediate 
macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199
 2012-10-04 04:03:53 +00:00
Akira Hatanaka
e1beddb7e8 Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether 
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071
 2012-07-31 19:13:07 +00:00
Akira Hatanaka
4a17cb84f3 Change name of class MipsInst to InstSE to distinguish it from mips16's 
instruction class. SE stands for standard encoding.

llvm-svn: 161069
 2012-07-31 18:55:01 +00:00
Akira Hatanaka
2a600ff5f4 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
 2012-05-22 03:10:09 +00:00
Akira Hatanaka
ecb1cd1ce4 Add disassembler to MIPS. 
Patch by Vladimir Medic. 

llvm-svn: 154935
 2012-04-17 18:03:21 +00:00
Akira Hatanaka
cecb440c11 Revert r153924. There were buildbot failures. 
llvm-svn: 153925
 2012-04-03 02:51:09 +00:00