Michael Liao
59114df23b
Add support of RTM from TSX extension
...
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
llvm-svn: 167573
2012-11-08 07:28:54 +00:00
Chad Rosier
651ecf255c
[ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] is
...
equivalent to [expr1 + expr2]. See test cases for more examples.
rdar://12470392
llvm-svn: 166949
2012-10-29 18:01:54 +00:00
Chad Rosier
3935e5ec30
Tell llvm-mc we're using intel syntax, so we don't have to use directives.
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llvm-svn: 166640
2012-10-24 23:34:38 +00:00
Chad Rosier
492e58a0f7
[ms-inline asm] Add back-end test case for r166632. Make sure we emit the
...
correct .s output as well as get the correct encoding by the integrated
assembler.
llvm-svn: 166638
2012-10-24 23:10:28 +00:00
Benjamin Kramer
1d2b1ffd35
X86: Depending on the local semantics of .align this test can also emit a nopl instead of nopw.
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llvm-svn: 165880
2012-10-13 17:38:00 +00:00
Benjamin Kramer
80915069f7
X86: Disable long nops for all cpus prior to pentiumpro/i686.
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llvm-svn: 165878
2012-10-13 17:28:35 +00:00
NAKAMURA Takumi
12cdeb840a
llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.
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-mcpu doesn't infer -arch. Consider non-x86 host.
llvm-svn: 164185
2012-09-19 00:56:20 +00:00
Roman Divacky
30a607bf14
Add test for r164132.
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llvm-svn: 164134
2012-09-18 16:19:10 +00:00
Chad Rosier
f7b609f0fb
Add newline.
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llvm-svn: 163565
2012-09-10 23:09:27 +00:00
Chad Rosier
e1355ead98
[ms-inline asm] Add support for .att_syntax directive.
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llvm-svn: 163542
2012-09-10 20:54:39 +00:00
Jim Grosbach
6d3cb70105
X86: Fix encoding of 'movd %xmm0, %rax'
...
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.
llvm-svn: 162963
2012-08-31 00:30:30 +00:00
Craig Topper
9667d599eb
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
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llvm-svn: 160775
2012-07-26 07:48:28 +00:00
Craig Topper
b144f3b6db
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
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llvm-svn: 160420
2012-07-18 04:11:12 +00:00
Craig Topper
b346ce8240
Reverse assembler/disassembler operand order for gather instructions.
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llvm-svn: 159983
2012-07-10 06:38:33 +00:00
Craig Topper
6fcb4454a0
Add aliases for pblendvb, blendvpd, and blendvps instructions with the implicit xmm0 operand specified. Fixes PR13252.
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llvm-svn: 159644
2012-07-03 05:49:45 +00:00
Manman Ren
63bf58865a
X86: add more GATHER intrinsics in LLVM
...
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
llvm-svn: 159402
2012-06-29 00:54:20 +00:00
Manman Ren
6be46b7b4c
X86: add GATHER intrinsics (AVX2) in LLVM
...
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
Craig Topper
5c8bdeb3f3
Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead.
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llvm-svn: 159184
2012-06-26 04:12:49 +00:00
Benjamin Kramer
0c823ae0ed
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
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This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
2012-05-29 19:05:25 +00:00
Charles Davis
a5e1970cd0
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
...
ret instructions.
llvm-svn: 154468
2012-04-11 01:10:53 +00:00
Craig Topper
ce6c05e0df
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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llvm-svn: 153935
2012-04-03 05:20:24 +00:00
Joerg Sonnenberger
82af1c8704
Fix generation of the address size override prefix. Add assertions for
...
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
llvm-svn: 153166
2012-03-21 05:48:07 +00:00
Kevin Enderby
b5413ed6cc
Change the X86 assembler to not require a segment register on string
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instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
llvm-svn: 152654
2012-03-13 19:47:55 +00:00
Kevin Enderby
9f26c75ab5
Added a missing error check for X86 assembly with mismatched base and index
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registers not both being 64-bit or both being 32-bit registers.
llvm-svn: 152580
2012-03-12 21:32:09 +00:00
Kevin Enderby
15f974a5a4
Add the missing call to Error when a bad X86 scale expression is parsed.
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llvm-svn: 152443
2012-03-09 22:24:10 +00:00
NAKAMURA Takumi
c97ffd132b
test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.
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llvm-svn: 152406
2012-03-09 14:52:38 +00:00
Eli Friedman
c397259ea6
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
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llvm-svn: 152136
2012-03-06 19:58:46 +00:00
Eli Friedman
4a049305a9
Make aliases for shld and shrd match gas. PR12173.
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llvm-svn: 152014
2012-03-05 04:31:54 +00:00
Kevin Enderby
4e089c2b5b
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
llvm-svn: 151267
2012-02-23 18:18:17 +00:00
Craig Topper
cfbfa3dcd1
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Craig Topper
ecf21d8132
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Eli Bendersky
4afdeeb682
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
...
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
llvm-svn: 150664
2012-02-16 06:28:33 +00:00
Devang Patel
be1817e3e0
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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llvm-svn: 149291
2012-01-30 22:47:12 +00:00
Devang Patel
a5bfdedb9f
Intel syntax. Support .intel_syntax directive.
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llvm-svn: 149270
2012-01-30 20:02:42 +00:00
Devang Patel
e4725ba181
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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llvm-svn: 149142
2012-01-27 19:48:28 +00:00
Devang Patel
0da753c9e6
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
...
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
Devang Patel
327773a25b
Intel syntax: Robustify parsing of memory operand's displacement experssion.
...
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Devang Patel
3c6289f43a
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Devang Patel
9698de5bf3
Intel syntax: Parse segment registers.
...
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
Devang Patel
0ecda3fc14
Intel syntax: Robustify register parsing.
...
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
Devang Patel
0638a44a24
Intel syntax: Parse ... PTR [-8]
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llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
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llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Devang Patel
b42cea31aa
Post process 'and', 'sub' instructions and select better encoding, if available.
...
llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Devang Patel
27ef211648
Intel syntax: There is no need to create unary expr for simple negative displacement.
...
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel
999eaa4b85
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
...
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Devang Patel
ee49d825b1
Process instructions after match to select alternative encoding which may be more desirable.
...
llvm-svn: 148431
2012-01-18 22:42:29 +00:00
Devang Patel
e03a4f051f
Intel syntax: Fix parser match class to check memory operand size.
...
llvm-svn: 148338
2012-01-17 21:48:03 +00:00
Devang Patel
4585b536ee
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
...
llvm-svn: 148334
2012-01-17 21:25:10 +00:00
Devang Patel
388aa8feb0
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
...
llvm-svn: 148321
2012-01-17 19:08:07 +00:00
Devang Patel
84d275a823
Intel syntax: Ignore mnemonic aliases.
...
llvm-svn: 148316
2012-01-17 18:30:45 +00:00
Devang Patel
b1e07175c4
Intel syntax: Robustify memory operand parsing.
...
llvm-svn: 148312
2012-01-17 18:00:18 +00:00
Devang Patel
79b7ed0c82
Add new test.
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llvm-svn: 148128
2012-01-13 18:45:31 +00:00
Devang Patel
807fee533d
Remove test case, as Chris suggested.
...
llvm-svn: 148039
2012-01-12 19:54:02 +00:00
Devang Patel
3f85289ef8
Add test case to check intel syntax parsing.
...
llvm-svn: 148034
2012-01-12 18:40:46 +00:00
Eli Friedman
f626b19bda
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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llvm-svn: 146709
2011-12-15 23:46:18 +00:00
Jan Sjödin
b9e2da0d9a
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
Jan Sjödin
2dfb343ffa
Support for encoding all FMA4 instructions and tablegen patterns for all
...
remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
Bruno Cardoso Lopes
626d04cc6f
This patch contains support for encoding FMA4 instructions and
...
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
Benjamin Kramer
d03fc374bd
X86: alias cqo to cqto.
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llvm-svn: 145121
2011-11-24 12:02:46 +00:00
Rafael Espindola
dd7a1f625b
Move test to the X86 directory, note the PR number and only run MC once.
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llvm-svn: 143352
2011-10-31 17:23:09 +00:00
Kevin Enderby
837c1d56a2
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
...
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
llvm-svn: 143112
2011-10-27 17:40:41 +00:00
Craig Topper
3cb62dca0f
Add X86 SARX, SHRX, and SHLX instructions.
...
llvm-svn: 142779
2011-10-23 22:18:24 +00:00
Craig Topper
0e63b4485c
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
Craig Topper
b1fa647871
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
...
llvm-svn: 142480
2011-10-19 07:48:35 +00:00
Craig Topper
6c900d9810
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
Craig Topper
2cd868184c
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Chris Lattner
321335142c
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
...
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
Craig Topper
4c6357d4af
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
Craig Topper
62e63d9bb9
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Kevin Enderby
974c799a5a
Finish supporting cpp #file/line comments in assembler for error messages. So
...
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
llvm-svn: 141814
2011-10-12 21:38:39 +00:00
Craig Topper
f083691b6d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
...
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
Craig Topper
2614f6f120
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
...
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
Bruno Cardoso Lopes
906f64c461
The wrong relocation was being emitted for several SSSE3 instructions.
...
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
Bruno Cardoso Lopes
de0dc10d6d
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
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llvm-svn: 140098
2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes
9979e44f1b
Re-write part of VEX encoding logic, to be more easy to read! Also fix
...
a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
Bruno Cardoso Lopes
306110c29a
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
...
implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
Bruno Cardoso Lopes
1e817d1451
Reorder declarations of vmovmskp* and also put the necessary AVX
...
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
Evan Cheng
04762a3cf5
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
...
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Kevin Enderby
9adbbfffd0
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
...
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
llvm-svn: 136287
2011-07-27 23:01:50 +00:00
Kevin Enderby
59ba10f2ac
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
...
push with a small constant produces a 2-byte push.
llvm-svn: 134501
2011-07-06 17:23:46 +00:00
Eli Friedman
9765ae0015
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
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llvm-svn: 134424
2011-07-05 18:21:20 +00:00
Joerg Sonnenberger
708b6e085d
Recognize the xstorerng alias for VIA PadLock's xstore instruction.
...
llvm-svn: 134126
2011-06-30 01:38:03 +00:00
Eli Friedman
802029c494
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
...
llvm-svn: 133759
2011-06-23 21:07:47 +00:00
Nick Lewycky
8e5c09b7dc
Add support for assembling "movq" when it's correct to do so, while continuing
...
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
llvm-svn: 133565
2011-06-21 22:45:41 +00:00
Bob Wilson
5b04895bb8
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
...
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
llvm-svn: 133524
2011-06-21 17:35:13 +00:00
Nick Lewycky
831fb8200d
Emit movq for 64-bit register to XMM register moves, but continue to accept
...
movd when assembling.
llvm-svn: 133452
2011-06-20 18:33:26 +00:00
Bill Wendling
5ae6b0c972
Improve the heuristic to emit the alias if the number of hard-coded registers
...
are also greater than the alias.
llvm-svn: 133038
2011-06-15 04:31:19 +00:00
Bill Wendling
77d4d62693
Heuristic: If the number of operands in the alias are more than the number of
...
operands in the aliasee, don't print the alias.
llvm-svn: 132963
2011-06-14 03:17:20 +00:00
Chris Lattner
859ce35115
add test from PR9164
...
llvm-svn: 131876
2011-05-22 22:35:34 +00:00
Chris Lattner
009caa6b41
testcase for PR9378
...
llvm-svn: 131875
2011-05-22 22:32:53 +00:00
Eric Christopher
4f90f378ee
Remove some random comments that snuck in from somewhere.
...
llvm-svn: 130812
2011-05-04 00:48:02 +00:00
Eric Christopher
1de0dfaab0
xmm0 is an implicit parameter in this and so shouldn't be in the
...
string template.
Fixes rdar://8493866
llvm-svn: 130747
2011-05-03 01:28:32 +00:00
Joerg Sonnenberger
42c3063de0
Add encoding tests for flds/filds
...
llvm-svn: 129589
2011-04-15 19:25:31 +00:00
Bill Wendling
0b9c16295a
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
...
(movzx/movsx) because they give more information. Revert that part of the patch.
llvm-svn: 129498
2011-04-14 01:46:37 +00:00
Bill Wendling
d49591cf21
Have the X86 back-end emit the alias instead of what's being aliased. In most
...
cases, it's much nicer and more informative reading the alias.
llvm-svn: 129497
2011-04-14 01:11:51 +00:00
Chris Lattner
b9b420d588
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
...
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
llvm-svn: 129223
2011-04-09 19:41:05 +00:00
Joerg Sonnenberger
1cbd300346
Add support for the VIA PadLock instructions.
...
llvm-svn: 128826
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
aa8ac259e9
Support explicit argument forms for the X86 string instructions.
...
For now, only the default segments are supported.
llvm-svn: 127875
2011-03-18 11:59:40 +00:00
Eli Friedman
7243ca7572
Followup to r126970: add 64-bit encoding tests for str with reg operand.
...
llvm-svn: 126987
2011-03-04 04:06:47 +00:00
Eli Friedman
be07c34368
PR9377: Handle x86 str with register operand in a way consistent with gas.
...
llvm-svn: 126970
2011-03-04 00:10:17 +00:00