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Author SHA1 Message Date
Jakob Stoklund Olesen
2611cc2520 Fix -widen-vmovs liveness issues. 
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746
 2011-10-12 00:06:23 +00:00
Evan Cheng
5b4ab71b44 Refine r141689 with a tri-state variable. 
Also teach MachineLICM to avoid "speculation" when register pressure is high.

llvm-svn: 141744
 2011-10-11 23:48:44 +00:00
Akira Hatanaka
ab6aae33e9 Change name of class to ArithOverflowR. 
llvm-svn: 141743
 2011-10-11 23:43:48 +00:00
Akira Hatanaka
5273f6aabb Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.

llvm-svn: 141742
 2011-10-11 23:38:52 +00:00
Bob Wilson
20cc1d9f51 Make this test more specific. There are 3 stats that matched "machine-licm". 
llvm-svn: 141741
 2011-10-11 23:34:31 +00:00
Eric Christopher
f19ddd9ae9 Use public accessors on the scope that is returned. 
llvm-svn: 141739
 2011-10-11 23:19:35 +00:00
Akira Hatanaka
0d687917ae Fix comment. 
llvm-svn: 141737
 2011-10-11 23:12:12 +00:00
Akira Hatanaka
12da673e60 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
 2011-10-11 23:05:46 +00:00
Chris Lattner
0d2ef52b69 target data is a contract with the code generator, not the "processor" 
llvm-svn: 141734
 2011-10-11 23:02:17 +00:00
Chris Lattner
9795434c0b improve some of the documentation around target data layout strings. 
llvm-svn: 141733
 2011-10-11 23:01:39 +00:00
Eric Christopher
57c57a3260 Add a new wrapper node for a DILexicalBlock that encapsulates it and a 
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.

This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.

Part of rdar://10246360

llvm-svn: 141729
 2011-10-11 22:59:11 +00:00
Eric Christopher
22773143e0 Formatting. 
llvm-svn: 141728
 2011-10-11 22:59:04 +00:00
Eric Christopher
a715203dda Spacing. 
llvm-svn: 141727
 2011-10-11 22:58:58 +00:00
Bill Wendling
f8cd4fcba7 N.B. This is with the new EH scheme: 
The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.

I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.

llvm-svn: 141726
 2011-10-11 22:42:31 +00:00
Akira Hatanaka
8a43300a4f Fix function isUnalignedLoadStore. 
llvm-svn: 141722
 2011-10-11 22:04:01 +00:00
Jim Grosbach
d2cfc2b31f ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
 2011-10-11 21:55:36 +00:00
Akira Hatanaka
4ea17fffd6 Remove unused PatLeaf. 
llvm-svn: 141720
 2011-10-11 21:53:08 +00:00
Akira Hatanaka
99550c035f Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.

llvm-svn: 141718
 2011-10-11 21:48:01 +00:00
Bill Wendling
a1c238d8bf Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... 
llvm-svn: 141716
 2011-10-11 21:40:47 +00:00
Akira Hatanaka
7ae83fe86a Remove redundancy in setcc patterns using multiclass. 
llvm-svn: 141715
 2011-10-11 21:40:01 +00:00
Cameron Zwarich
fac176ac51 Fix PR11106 by correcting a typo that has been in the code for over a year. This 
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.

llvm-svn: 141713
 2011-10-11 21:26:40 +00:00
Akira Hatanaka
f8aabd951e Use sltiu instead of sltu when a register operand and immediate are compared. 
llvm-svn: 141708
 2011-10-11 20:44:43 +00:00
Jim Grosbach
313a74d565 Update test for r141704. 
llvm-svn: 141705
 2011-10-11 20:18:50 +00:00
Jim Grosbach
66bf42f4bb ARM addressing mode cleanup for LDC/STC. 
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

llvm-svn: 141704
 2011-10-11 20:17:35 +00:00
Daniel Dunbar
48c24625fe Clean up a few references to System/. We still have docs/SystemLibrary.html 
lying around...

llvm-svn: 141703
 2011-10-11 20:02:52 +00:00
Daniel Dunbar
2b6c2310cd Support/DataTypes.h: Clean up some types and add matching (but presumably 
unused) code from .cmake to DataTypes.h.in so that the files are essentially in
sync module differences in autoconf/cmake replacement syntax.

llvm-svn: 141702
 2011-10-11 20:02:49 +00:00
Eli Friedman
0a06205b37 Remove extra semicolon. 
llvm-svn: 141699
 2011-10-11 19:53:40 +00:00
Akira Hatanaka
27c0f84dce Add patterns for conditional branches with 64-bit register operands. 
llvm-svn: 141696
 2011-10-11 19:09:09 +00:00
Akira Hatanaka
1594be76f8 Add support for 64-bit set-on-less-than instructions. 
llvm-svn: 141695
 2011-10-11 18:53:46 +00:00
Akira Hatanaka
9df92e48e1 Add support for conditional branch instructions with 64-bit register operands. 
llvm-svn: 141694
 2011-10-11 18:49:17 +00:00
Devang Patel
3811b42be0 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689
 2011-10-11 18:09:58 +00:00
Lang Hames
77c4f6fc53 Fixed docs to reflect the proper default value and behaviour of the natural stack alignment. 
llvm-svn: 141687
 2011-10-11 17:50:14 +00:00
Owen Anderson
85292f7b5d Expose MachOObjectFile externally, like we do for COFF. First step in reducing the amount of special-purpose code needed for llvm-objdump. 
llvm-svn: 141684
 2011-10-11 17:32:27 +00:00
Jim Grosbach
a4d00441c7 ARM parse alignment specifier for NEON load/store instructions. 
llvm-svn: 141682
 2011-10-11 17:29:55 +00:00
Duncan Sands
9f61f160f8 Mention the cmake build guide on the main docs page. 
llvm-svn: 141674
 2011-10-11 16:35:07 +00:00
Jim Grosbach
556c9f6f6c ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity. 
llvm-svn: 141671
 2011-10-11 15:59:20 +00:00
Nadav Rotem
6ddbd1308b Add support for legalization of vector SHL/SRA/SRL instructions 
llvm-svn: 141667
 2011-10-11 14:36:35 +00:00
Richard Osborne
ca9b871ab7 Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks. 
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).

llvm-svn: 141666
 2011-10-11 12:55:35 +00:00
Kalle Raiskila
19b09a39e2 Fix a iterator out of bounds error, that triggers rarely. 
llvm-svn: 141665
 2011-10-11 12:55:18 +00:00
NAKAMURA Takumi
bf2fb9b9e2 llvm-objdump.cpp: Use PRIx64 as format specifier for int64_t. 
llvm-svn: 141664
 2011-10-11 12:51:50 +00:00
NAKAMURA Takumi
162abf56c1 Add -D__STDC_FORMAT_MACROS to use PRIx64. 
llvm-svn: 141663
 2011-10-11 12:51:44 +00:00
NAKAMURA Takumi
aebe963472 cmake/modules/HandleLLVMOptions.cmake: Reorder __STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS. 
llvm-svn: 141662
 2011-10-11 12:51:36 +00:00
Nadav Rotem
451cacafa0 Add support for legalization of vector trunc-store where the saved scalar type is illegal (for example, v2i16 on systems where the smallest store size is i32) 
llvm-svn: 141661
 2011-10-11 11:25:16 +00:00
Nadav Rotem
45b5fc0012 Cleanup the trunc-store legalization code and add asserts. 
llvm-svn: 141659
 2011-10-11 10:04:25 +00:00
Bill Wendling
bdbb880377 Update to a newer doxygen version. PR8214. Patch by Jeremy Huddleston. 
llvm-svn: 141657
 2011-10-11 07:25:38 +00:00
Craig Topper
881d972428 Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. 
llvm-svn: 141656
 2011-10-11 07:13:09 +00:00
Bill Wendling
aeb63260c7 Minor modifications to make the Hello World example resemble the Hello World 
pass in the tree. Also some minor formatting changes.
PR9413

llvm-svn: 141655
 2011-10-11 07:03:52 +00:00
Craig Topper
db2d702bff Make Ivy Bridge 16-bit floating point conversion instructions require AVX. 
llvm-svn: 141654
 2011-10-11 07:01:37 +00:00
Nick Lewycky
6bd023fab9 Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.

llvm-svn: 141653
 2011-10-11 06:58:11 +00:00
Craig Topper
f95d9bd513 Test case for X86 LZCNT instruction selection. 
llvm-svn: 141652
 2011-10-11 06:47:01 +00:00