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Commit Graph

192018 Commits

Author SHA1 Message Date
Simon Tatham
270ded9a96 [TableGen] Don't elide bitconverts in PatFrag fragments.
Summary:
In the DAG pattern backend, `SimplifyTree` simplifies a pattern by
removing bitconverts between two identical types. But that function is
also run on the fragments list in instances of `PatFrags`, in which
the types haven't been specified yet. So the input and output of the
bitconvert always evaluate to the empty set of types, which makes them
compare equal. So the test always passes, and bitconverts are
unconditionally removed from the PatFrag RHS.

Fixed by spotting the empty type set and using it to inhibit the
optimization.

Reviewers: nhaehnle, hfinkel

Reviewed By: nhaehnle

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74627
2020-02-17 09:30:45 +00:00
Sourabh Singh Tomar
743f6f19e1 [NFCI][DebugInfo]: Corrected a Typo. 2020-02-17 14:50:32 +05:30
Sjoerd Meijer
98e5ebee08 [X86] New test to check rev16 patterns, prep step for D74032. NFC. 2020-02-17 09:13:21 +00:00
Kang Zhang
11e984b94f [NFC][PowerPC] Update the test case scalar-equal.ll
Modify the command option to add --enable-no-nans-fp-math
2020-02-17 08:34:56 +00:00
Fangrui Song
8704181812 [MC] Delete two unused MCCodePadder functions missed by D71106 2020-02-16 22:37:33 -08:00
QingShan Zhang
31dbc630ba [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions
We have the InstAlias rules for 32-bit rotate but missing the 64-bit one.
Rotate left immediate rotlwi ra,rs,n rlwinm ra,rs,n,0,31
Rotate left rotlw ra,rs,rb rlwnm ra,rs,rb,0,31

Differential Revision: https://reviews.llvm.org/D72676
2020-02-17 05:42:49 +00:00
Kang Zhang
b05eadcb6d [NFC][PowerPC] Add a new test case scalar-equal.ll 2020-02-17 05:27:36 +00:00
Michael Liao
178676a0af Fix -Wpedantic warning. NFC. 2020-02-17 00:18:01 -05:00
Craig Topper
d62deed2bc [X86] Disable load folding for X86ISD::ADD with 128 as an immediate.
It can be turned into a sub with -128 instead as long as the
carry flag isn't used.
2020-02-16 20:52:51 -08:00
Craig Topper
e00c9e9b99 [X86] Remove unnecessary check for null SDValue. NFC 2020-02-16 20:25:24 -08:00
Matt Arsenault
8183f0968e AMDGPU/GlobalISel: Fix non-power-of-2 G_SITOFP/G_UITOFP
This wouldn't work for s33-s63 sources.
2020-02-16 22:48:57 -05:00
Matt Arsenault
269134b058 AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases 2020-02-16 22:48:42 -05:00
Matt Arsenault
8eebd129ef AMDGPU/GlobalISel: Move lambdas to normal function
These aren't using any local state
2020-02-16 22:48:32 -05:00
Nico Weber
b4c3361d6d [gn build] use -Xclang form for fdebug-comp-dir for now
The driver version of the flag seems to confuse goma.
2020-02-16 21:30:27 -05:00
Zheng Chen
136d9afbf0 [Powerpc] set instruction count as lsr first priority of lsr.
On Powerpc, set instruction count as lsr first priority of lsr by default.
Add an option ppc-lsr-no-insns-cost to return back to default lsr cost model.

Reviewed By: steven.zhang, jsji

Differential Revision: https://reviews.llvm.org/D72683
2020-02-16 21:04:55 -05:00
Craig Topper
11c8ae2f75 [X86] Increase latency of port5 masked compares and kshift/kadd/kunpck instructions in SKX scheduler model
Uops.info shows these as 4 cycle latency.
2020-02-16 16:59:37 -08:00
Craig Topper
04d909f9da [X86] Add more avx512 instrutions to llvm-mca resource tests 2020-02-16 16:59:36 -08:00
Fangrui Song
818e7cf223 [IR] Change maybeSetDSOLocal to isImplicitDSOLocal
This allows some simplification.
2020-02-16 13:14:15 -08:00
Florian Hahn
0338a099fe [SCCP] Re-generate check lines using --function-signature. (NFC) 2020-02-16 20:34:54 +01:00
Craig Topper
9652cb2bdf [X86] Separate floating point handling out of EmitCmp and emitFlagsForSetcc.
Both of those functions only have a single caller starting
at LowerSETCC. Just handle floating point directly in LowerSETCC.

This removes the need to pass Chain and IsSignaling all the way
down.
2020-02-16 10:51:05 -08:00
Craig Topper
de5f34315e [X86] Split X86ISD::CMP into an integer and FP opcode. 2020-02-16 10:10:19 -08:00
LLVM GN Syncbot
c716c3ff18 [gn build] Port ee2c0f76d74 2020-02-16 17:32:06 +00:00
Eric Astor
ca668acee6 [ms] [llvm-ml] Add a draft MASM parser
Summary:
Many directives are unavailable, and support for others may be limited.

This first draft has preliminary support for:
    - conditional directives (including errors),
    - data allocation (unsigned types up to 8 bytes, and ALIGN),
    - equates/variables (numeric and text),
    - and procedure directives (without parameters),
as well as COMMENT, ECHO, INCLUDE, INCLUDELIB, PUBLIC, and EXTERN. Text variables (aka text macros) are expanded in-place wherever the identifier occurs.

We deliberately ignore all ml.exe processor directives.

Prominent features not yet supported:
    - structs
    - macros (both procedures and functions)
    - procedures (with specified parameters)
    - substitution & expansion operators

Conditional directives are complicated by the fact that "ifdef rax" is a valid way to check if a file is being assembled for a 64-bit x86 processor; we add support for "ifdef <register>" in general, which requires adding a tryParseRegister method to all MCTargetAsmParsers. (Some targets require backtracking in the non-register case.)

Reviewers: rnk, thakis

Reviewed By: thakis

Subscribers: kerbowa, merge_guards_bot, wuzish, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, mgorny, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72680
2020-02-16 12:30:46 -05:00
Nikita Popov
8b20125228 [IRBuilder] Prefer InsertPointGuard over full copy; NFC
Don't copy the IRBuilder when an InsertPointGuard would also do.
2020-02-16 18:02:29 +01:00
Nikita Popov
d43d09bc84 [IRBuilder] Fix unnecessary IRBuilder copies; NFC
Fix a few cases where an IRBuilder is passed to a helper function
by value, while a by reference pass was intended.
2020-02-16 17:57:18 +01:00
Simon Pilgrim
dd8d9953a0 [X86] combineX86ShuffleChain - add support for combining 512-bit shuffles to PALIGNR 2020-02-16 16:13:26 +00:00
Simon Pilgrim
d3230253b1 [X86] combineX86ShuffleChain - add support for combining 512-bit shuffles to bit shifts 2020-02-16 16:13:25 +00:00
Nikita Popov
163465c064 Revert "[IRBuilder] Virtualize IRBuilder"
This reverts commit 0765d3824d069f37596bc5a890399099b776c2a0.
This reverts commit 1b04866a3db9f816a559860f941da067fe1eccf1.

Relevant looking crashes observed on:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win
2020-02-16 17:01:10 +01:00
Sanjay Patel
ace163be2a [VectorCombine] fix cost calc for extract-cmp
getOperationCost() is not the cost we wanted; that's not the
throughput value that the rest of the calculation uses.

We may want to switch everything in this code to use the
getInstructionThroughput() wrapper to avoid these kinds of
problems, but I'll look at that as a follow-up because that
can create other logical diffs via using optional parameters
(we'd need to speculatively create the vector instruction to
make a fair(er) comparison).
2020-02-16 10:40:28 -05:00
Sanjay Patel
e1da7dc606 [x86] form broadcast of scalar memop even with >1 use
The unseen logic diff occurs because MayFoldLoad() is defined like this:

static bool MayFoldLoad(SDValue Op) {
  return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
}

The test diffs here all seem ok to me on screen/paper, but it's hard to know
if that will lead to universally better perf for all targets. For example,
if a target implements broadcast from mem as multiple uops, we would have to
weigh the potential reduction of instructions and register pressure vs.
possible increase in number of uops. I don't know if we can make a truly
informed decision on this at compile-time.

The motivating case that I'm looking at in PR42024:
https://bugs.llvm.org/show_bug.cgi?id=42024
...resembles the diff in extract-concat.ll, but we're not going to change the
larger example there without at least 1 other fix.

Differential Revision: https://reviews.llvm.org/D74088
2020-02-16 10:32:56 -05:00
Nikita Popov
344cb40499 [InstCombine] Create new log2 intrinsic; NFCI
Rather than mixing creation of new instructions and in-place
modification here, create a new log2 intrinsic. This should be
NFC apart from worklist order changes.
2020-02-16 15:52:09 +01:00
Nikita Popov
f51c934143 [InstCombine] Add multiuse tests for cttz transform; NFC
These show incorrect duplication of instructions.
2020-02-16 15:52:09 +01:00
Nikita Popov
16d8ab7026 [IRBuilder] Try to fix warnings
Try to fix -Wnon-virtual-dtor warnings that cause build failure
on clang-pcc64le-rhel.
2020-02-16 15:32:11 +01:00
Nikita Popov
f3c97cd987 [IRBuilder] Virtualize IRBuilder
Related llvm-dev thread:
http://lists.llvm.org/pipermail/llvm-dev/2020-February/138951.html

This patch moves the IRBuilder from templating over the constant
folder and inserter towards making both of these virtual.
There are a couple of motivations for this:

1. It's not possible to share code between use-sites that use
different IRBuilder folders/inserters (short of templating the code
and moving it into headers).
2. Methods currently defined on IRBuilderBase (which is not templated)
do not use the custom inserter, resulting in subtle bugs (e.g.
incorrect InstCombine worklist management). It would be possible to
move those into the templated IRBuilder, but...
3. The vast majority of the IRBuilder implementation has to live
in the header, because it depends on the template arguments.
4. We have many unnecessary dependencies on IRBuilder.h,
because it is not easy to forward-declare. (Significant parts of
the backend depend on it via TargetLowering.h, for example.)

This patch addresses the issue by making the following changes:

* IRBuilderDefaultInserter::InsertHelper becomes virtual.
  IRBuilderBase accepts a reference to it.
* IRBuilderFolder is introduced as a virtual base class. It is
 implemented by ConstantFolder (default), NoFolder and TargetFolder.
  IRBuilderBase has a reference to this as well.
* All the logic is moved from IRBuilder to IRBuilderBase. This means
  that methods can in the future replace their IRBuilder<> & uses
  (or other specific IRBuilder types) with IRBuilderBase & and thus
  be usable with different IRBuilders.
* The IRBuilder class is now a thin wrapper around IRBuilderBase.
  Essentially it only stores the folder and inserter and takes care
  of constructing the base builder.

What this patch doesn't do, but should be simple followups after this change:

* Fixing use of the inserter for creation methods originally defined
  on IRBuilderBase.
* Replacing IRBuilder<> uses in arguments with IRBuilderBase, where useful.
* Moving code from the IRBuilder header to the source file.

From the user perspective, these changes should be mostly transparent:
The only thing that consumers using a custom inserted may need to do is
inherit from IRBuilderDefaultInserter publicly and mark their InsertHelper
as public.

Differential Revision: https://reviews.llvm.org/D73835
2020-02-16 13:48:55 +01:00
Georgii Rymar
86793686ea [llvm-readobj] - Refactor the code that dumps relocations.
The current code has following issues:
1) It has a duplicated logic part.
2) This logic relies on unwrapOrError calls, but if we want to convert
   them to warnings, we will need to change all of them what is hard to do
   because of the duplication.

In this patch I've created a new method that returns Expected<> what allows
now to catch all errors in a single place and remove the code duplication.

Note: this change is itself a refactor NFC. It does not change the current logic
anyhow. It prepares the code for the follow-up(s).

Differential revision: https://reviews.llvm.org/D74545
2020-02-16 14:39:24 +03:00
Johannes Doerfert
0c3be93d04 [Attributor][FIX] Use pointer not reference as it can be null 2020-02-15 20:38:49 -06:00
Greg Clayton
0f9e8cbf13 [NFC] Move ValidTextRanges out of DwarfTransformer and into GsymCreator and unify address is not in GSYM errors so all strings match. 2020-02-15 16:48:23 -08:00
Simon Pilgrim
581191183a [X86] Add test cases showing failure to simplify target shuffles to bit shifts 2020-02-15 23:34:31 +00:00
Simon Pilgrim
fbb23f6a16 Fix Wdocumentation unknown parameter warnings. NFCI. 2020-02-15 23:33:17 +00:00
Simon Pilgrim
65f71cef2b [X86][AVX512] Split AVX512F and AVX512BW shuffle combining tests
Split off shuffle combine tests that use AVX512F intrinsics, so we can test it with/without AVX512BW support.
2020-02-15 22:48:52 +00:00
Fangrui Song
c5ceb65199 [X86][AsmPrinter] PrintSymbolOperand: prefer to lower ELF MO_GlobalAddress to .Lfoo$local 2020-02-15 13:45:29 -08:00
Florian Hahn
0c03d6c1a0 [ValueLattice] Update markConstantRange to return false equal ranges.
Currently we always return true, when markConstantRange is used on an
object already containing a constant range. If NewR is equal to the
existing constant range however, nothing changes and we should return
false.

I also went ahead and added a clarifying comment and improved the
assertion.

Reviewers: efriedma, davide, nikic

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D73240
2020-02-15 22:06:55 +01:00
Craig Topper
5dec6107a4 [X86] Merge two switches together to simplify some code. NFC 2020-02-15 12:55:51 -08:00
Craig Topper
d691bd34c9 [X86] Fix typo in comment. NFC 2020-02-15 12:48:19 -08:00
Simon Pilgrim
de7864d8a0 [X86] combineX86ShuffleChain - add support for combining to X86ISD::ROTLI
Refactors matchShuffleAsBitRotate to allow use by both lowerShuffleAsBitRotate and matchUnaryPermuteShuffle.
2020-02-15 20:04:54 +00:00
Florian Hahn
cbe8e4d716 [ValueLattice] Make mark* functions public, return if value changed.
This patch prepares ValueLatticeElement to be used by SCCP, by:
* making the mark* functions public
* make the mark* functions return a bool indicating if the value has changed.

Reviewers: efriedma, davide, mssimpso, nikic

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D60581
2020-02-15 20:54:58 +01:00
Simon Pilgrim
43c6ded458 [X86] Add test showing failure to combine shuffle to bit rotation 2020-02-15 19:23:00 +00:00
Craig Topper
3dabf9d8ed [X86] Move combineIncDecVector logic from Select to PreprocessISelDAG.
This allows it to work properly with masked inc/dec for avx512. Those
would have a vselect as the root node so didn't get a chance to call
combineIncDecVector.

This also simplifies the logic because we don't have to manage
the topological ordering.
2020-02-15 09:59:12 -08:00
Florian Hahn
61a834b1e0 Recommit "[SCCP] Remove forcedconstant, go to overdefined instead"
This includes a fix for cases where things get marked as overdefined in
ResolvedUndefsIn, but we later discover a constant. To avoid crashing,
we consistently bail out on overdefined values in the visitors. This is
similar to the previous behavior with forcedconstant.

This reverts the revert commit 02b72f564c8be0b4f4337d5c4a3fcf7e8018a818.
2020-02-15 18:36:44 +01:00
Fangrui Song
181d5382b7 [MC] De-capitalize MCStreamer::Emit{Bundle,Addrsig}* etc
So far, all non-COFF-related Emit* functions have been de-capitalized.
2020-02-15 09:11:48 -08:00