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Commit Graph

78 Commits

Author SHA1 Message Date
Manman Ren
edc0da266c Debug Info Testing: use null instead of an empty string in context field.
llvm-svn: 190284
2013-09-09 00:12:17 +00:00
Manman Ren
450526b5a9 Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).

llvm-svn: 190205
2013-09-06 21:03:58 +00:00
Manman Ren
20ae2817fa Debug Info: add an identifier field to DICompositeType.
DICompositeType will have an identifier field at position 14. For now, the
field is set to null in DIBuilder.
For DICompositeTypes where the template argument field (the 13th field)
was optional, modify DIBuilder to make sure the template argument field is set.
Now DICompositeType has 15 fields.

Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode.
Update verifier to check that DICompositeType has 15 fields and the last
field is null or a MDString.

Update testing cases to include an extra field for DICompositeType.
The identifier field will be used by type uniquing so a front end can
genearte a DICompositeType with a unique identifer.

llvm-svn: 189282
2013-08-26 22:39:55 +00:00
Manman Ren
1b7973fc19 TBAA: remove !tbaa from testing cases when they are not needed.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 188944
2013-08-21 22:20:53 +00:00
Daniel Dunbar
a496d61c01 [tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

llvm-svn: 188513
2013-08-16 00:37:11 +00:00
Tim Northover
29e73e0f55 Refactor isInTailCallPosition handling
This change came about primarily because of two issues in the existing code.
Niether of:

define i64 @test1(i64 %val) {
  %in = trunc i64 %val to i32
  tail call i32 @ret32(i32 returned %in)
  ret i64 %val
}

define i64 @test2(i64 %val) {
  tail call i32 @ret32(i32 returned undef)
  ret i32 42
}

should be tail calls, and the function sameNoopInput is responsible. The main
problem is that it is completely symmetric in the "tail call" and "ret" value,
but in reality different things are allowed on each side.

For these cases:
1. Any truncation should lead to a larger value being generated by "tail call"
   than needed by "ret".
2. Undef should only be allowed as a source for ret, not as a result of the
   call.

Along the way I noticed that a mismatch between what this function treats as a
valid truncation and what the backends see can lead to invalid calls as well
(see x86-32 test case).

This patch refactors the code so that instead of being based primarily on
values which it recurses into when necessary, it starts by inspecting the type
and considers each fundamental slot that the backend will see in turn. For
example, given a pathological function that returned {{}, {{}, i32, {}}, i32}
we would consider each "real" i32 in turn, and ask if it passes through
unchanged. This is much closer to what the backend sees as a result of
ComputeValueVTs.

Aside from the bug fixes, this eliminates the recursion that's going on and, I
believe, makes the bulk of the code significantly easier to understand. The
trade-off is the nasty iterators needed to find the real types inside a
returned value.

llvm-svn: 187787
2013-08-06 09:12:35 +00:00
Manman Ren
d32ce58b2f Debug Info Verifier: verify SPs in llvm.dbg.sp.
Also always add DIType, DISubprogram and DIGlobalVariable to the list
in DebugInfoFinder without checking them, so we can verify them later
on.

llvm-svn: 187285
2013-07-27 01:26:08 +00:00
Manman Ren
c20620404a Debug Info: improve the verifier to check field types.
Make sure the context field of DIType is MDNode.
Fix testing cases to make them pass the verifier.

llvm-svn: 187150
2013-07-25 19:33:30 +00:00
Manman Ren
2abe20d1ee Debug Info: improve the Finder.
Improve the Finder to handle context of a DIVariable used by DbgValueInst.
Fix testing cases to make them pass the verifier.

llvm-svn: 187052
2013-07-24 17:10:09 +00:00
Stephen Lin
3ae734a60c Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.

llvm-svn: 186258
2013-07-13 20:38:47 +00:00
Jyotsna Verma
a1b968ec45 Hexagon: Pass to replace tranfer/copy instructions into combine instruction
where possible.

llvm-svn: 181817
2013-05-14 18:54:06 +00:00
Jyotsna Verma
980fae33f3 Hexagon: Add patterns to generate 'combine' instructions.
llvm-svn: 181805
2013-05-14 17:16:38 +00:00
Jyotsna Verma
86beda7e47 Hexagon: ArePredicatesComplement should not restrict itself to TFRs.
llvm-svn: 181803
2013-05-14 16:36:34 +00:00
Jyotsna Verma
a892e02220 Hexagon: Test case to check if branch probabilities are properly reflected in
the jump instructions in the form of taken/not-taken hint.

llvm-svn: 181799
2013-05-14 15:50:49 +00:00
Jyotsna Verma
2dfc0b2d13 Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
llvm-svn: 181624
2013-05-10 20:27:34 +00:00
Jyotsna Verma
15d448ba0c Hexagon: Use relation map for getMatchingCondBranchOpcode() and
getInvertedPredicatedOpcode() functions instead of switch cases.

llvm-svn: 181530
2013-05-09 18:25:44 +00:00
Jyotsna Verma
37863260ff Hexagon: Fix Small Data support to handle -G 0 correctly.
llvm-svn: 181344
2013-05-07 19:53:00 +00:00
Jyotsna Verma
5307666fe8 Reverting r181331.
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.

llvm-svn: 181334
2013-05-07 17:12:35 +00:00
Jyotsna Verma
af0c734e1b Hexagon: Fix Small Data support to handle -G 0 correctly.
llvm-svn: 181331
2013-05-07 16:42:15 +00:00
Pranav Bhandarkar
520d26e773 Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.

llvm-svn: 180946
2013-05-02 20:22:51 +00:00
Manman Ren
0b37dd0efc TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180796
2013-04-30 17:52:57 +00:00
Jyotsna Verma
4a5d195942 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.
llvm-svn: 180145
2013-04-23 21:17:40 +00:00
Jyotsna Verma
624f2e0434 Hexagon: Remove assembler mapped instruction definitions.
llvm-svn: 180133
2013-04-23 19:15:55 +00:00
Jyotsna Verma
20903a7aba Hexagon: Remove duplicate instructions to handle global/immediate values
for absolute/absolute-set addressing modes.

llvm-svn: 180120
2013-04-23 17:11:46 +00:00
Jyotsna Verma
f28cc49519 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.
llvm-svn: 178279
2013-03-28 19:34:49 +00:00
Jyotsna Verma
8a524534a6 Hexagon: Use multiclass for gp-relative instructions.
Remove noV4T gp-relative instructions.

llvm-svn: 178246
2013-03-28 16:25:57 +00:00
Jyotsna Verma
665c66e6ea Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
llvm-svn: 178032
2013-03-26 15:43:57 +00:00
Jyotsna Verma
fa7dec4e5b Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
llvm-svn: 177747
2013-03-22 18:41:34 +00:00
Jyotsna Verma
f2d3c71cf4 Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.

llvm-svn: 177103
2013-03-14 19:08:03 +00:00
Jyotsna Verma
6ba1f8e0d8 Hexagon: Add patterns for zero extended loads from i1->i64.
llvm-svn: 176689
2013-03-08 14:15:15 +00:00
Jyotsna Verma
50e5f420d7 Hexagon: Handle i8, i16 and i1 Var Args.
llvm-svn: 176647
2013-03-07 20:28:34 +00:00
Jyotsna Verma
c3d8f08545 Hexagon: Add support to lower block address.
llvm-svn: 176637
2013-03-07 19:10:28 +00:00
Jyotsna Verma
e27b88fb08 reverting patch 176508.
llvm-svn: 176513
2013-03-05 20:29:23 +00:00
Jyotsna Verma
ef3cf2b345 Hexagon: Add support for lowering block address.
llvm-svn: 176508
2013-03-05 19:37:46 +00:00
Jyotsna Verma
baf7212bfe Hexagon: Expand addc, adde, subc and sube.
llvm-svn: 176505
2013-03-05 19:04:47 +00:00
Jyotsna Verma
c096fbaa7d Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499
2013-03-05 18:42:28 +00:00
Jyotsna Verma
359daa8ad9 Hexagon: Add constant extender support framework.
llvm-svn: 176358
2013-03-01 17:37:13 +00:00
Anshuman Dasgupta
810cccb843 Hexagon: Expand cttz, ctlz, and ctpop for now.
llvm-svn: 175783
2013-02-21 19:39:40 +00:00
Jyotsna Verma
84136133e3 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.

llvm-svn: 175634
2013-02-20 16:13:27 +00:00
Anshuman Dasgupta
a6322b9e0a Hexagon: add support for predicate-GPR copies.
llvm-svn: 175102
2013-02-13 22:56:34 +00:00
Jyotsna Verma
a382dbb48f Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.

llvm-svn: 175086
2013-02-13 21:38:46 +00:00
Jyotsna Verma
abd979fd30 Hexagon: Add support to generate predicated absolute addressing mode
instructions.

llvm-svn: 174973
2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek
272abb00e0 Extend Hexagon hardware loop generation to handle various additional cases:
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

llvm-svn: 174904
2013-02-11 21:37:55 +00:00
Jyotsna Verma
31124b1816 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
2013-02-05 19:20:45 +00:00
Jyotsna Verma
a3fc230d1b Hexagon: Add testcase for post-increment store instructions.
llvm-svn: 174419
2013-02-05 18:23:51 +00:00
Jyotsna Verma
774837ab41 Hexagon: Use multiclass for absolute addressing mode stores.
llvm-svn: 174412
2013-02-05 18:15:34 +00:00
Jyotsna Verma
56ef42a2ac Hexagon: Add V4 compare instructions. Enable relationship mapping
for the existing instructions.

llvm-svn: 174389
2013-02-05 16:42:24 +00:00
Jyotsna Verma
e97a68f8b5 Hexagon: Add V4 combine instructions and some more Def Pats for V2.
llvm-svn: 174331
2013-02-04 15:52:56 +00:00
Jyotsna Verma
5e4467cefa Hexagon: Test case to confirm generation of indexed loads with zero offset.
llvm-svn: 174196
2013-02-01 16:40:06 +00:00
Jyotsna Verma
01c6fabba6 Add indexed load/store instructions for offset validation check.
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902

llvm-svn: 172737
2013-01-17 18:42:37 +00:00