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2df647f882
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2722 Commits

Author SHA1 Message Date
Dale Johannesen
2df647f882 Changes to ARM tail calls, mostly cosmetic. 
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
 2010-07-08 01:18:23 +00:00
Jim Grosbach
46d94f1c1e grammar 
llvm-svn: 107831
 2010-07-07 22:53:35 +00:00
Jim Grosbach
8f27ad0d9d Handle cases where the post-RA scheduler may move instructions between the 
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830
 2010-07-07 22:51:22 +00:00
Jim Grosbach
d13cc7716e grammar and trailing whitespace 
llvm-svn: 107811
 2010-07-07 21:06:51 +00:00
Dan Gohman
c768525273 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786
 2010-07-07 15:54:55 +00:00
Bob Wilson
822b21f0de Also use REG_SEQUENCE for VTBX instructions. 
llvm-svn: 107743
 2010-07-07 00:08:54 +00:00
Jim Grosbach
71b7efe8ad Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where 
they've been tested to work.

llvm-svn: 107742
 2010-07-07 00:07:57 +00:00
Jim Grosbach
657ab4a8ee By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734
 2010-07-06 23:44:52 +00:00
Bob Wilson
ce80768ebf Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be 
allocated to consecutive registers.

llvm-svn: 107730
 2010-07-06 23:36:25 +00:00
Jakob Stoklund Olesen
44c333e87c Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725
 2010-07-06 23:26:23 +00:00
Devang Patel
7ab104353b Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson
084a11cb59 Represent NEON load/store alignments in bytes, not bits. 
llvm-svn: 107701
 2010-07-06 21:26:18 +00:00
Dan Gohman
808f334f79 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Rafael Espindola
e5689571a1 Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion 
if profitable.

llvm-svn: 107673
 2010-07-06 16:24:34 +00:00
Dan Gohman
4d264f7e51 Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman
6a73079aba Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00
Evan Cheng
47f3a2db40 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
llvm-svn: 107550
 2010-07-03 00:40:23 +00:00
Evan Cheng
8c4e6ba789 Remove early IT block formation. It's not used. 
llvm-svn: 107513
 2010-07-02 21:07:09 +00:00
Bob Wilson
f96aab3079 Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so 
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

llvm-svn: 107487
 2010-07-02 17:23:44 +00:00
Bob Wilson
17dc7d716b ARM function alignments were off by a power of two. svn 83242 changed 
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.

llvm-svn: 107435
 2010-07-01 22:26:26 +00:00
Bob Wilson
1b4210315e Add support for encoding VDUP (ARM core register) instructions. 
llvm-svn: 107201
 2010-06-29 20:13:29 +00:00
Bob Wilson
be81c92b41 Add support for encoding NEON VMOV (from core register to scalar) instructions. 
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167
 2010-06-29 17:34:07 +00:00
Jim Grosbach
151bec3c2d skip dbg_value instructions 
llvm-svn: 107154
 2010-06-29 16:55:24 +00:00
Bob Wilson
74996289e3 The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add 
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

llvm-svn: 107147
 2010-06-29 16:25:11 +00:00
Rafael Espindola
832e4ddde7 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses 
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

llvm-svn: 107140
 2010-06-29 14:02:34 +00:00
Duncan Sands
1a45e3dbce Remove pointless variable LastDef. 
llvm-svn: 107135
 2010-06-29 13:23:22 +00:00
Duncan Sands
9eff796264 Remove unused variable Loc and pointless variables unified_syntax 
and thumb_mode.

llvm-svn: 107133
 2010-06-29 13:04:35 +00:00
Duncan Sands
25a2d02c5c Remove an unused and a pointless variable. 
llvm-svn: 107131
 2010-06-29 13:00:29 +00:00
Duncan Sands
b955b3bf92 Remove initialized but otherwise unused variables. 
llvm-svn: 107127
 2010-06-29 11:22:26 +00:00
Evan Cheng
6349fa5ec4 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. 
llvm-svn: 107122
 2010-06-29 05:38:36 +00:00
Evan Cheng
9883684f03 Change if-cvt options to something that actually as useable. 
llvm-svn: 107121
 2010-06-29 05:37:59 +00:00
Jakob Stoklund Olesen
b72b136170 When no memoperands are present, assume unaligned, volatile. 
llvm-svn: 107114
 2010-06-29 01:13:07 +00:00
Bob Wilson
2a4e6d0e34 Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is 
the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107
 2010-06-29 00:26:13 +00:00
Bob Wilson
aee90dacaa Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead 
of the Subtarget.

llvm-svn: 107086
 2010-06-28 22:23:17 +00:00
Jim Grosbach
8441e67098 tidy up style. no functional change. 
llvm-svn: 107073
 2010-06-28 21:29:17 +00:00
Bob Wilson
378395412f Refactor encoding function for NEON 1-register with modified immediate format. 
llvm-svn: 107070
 2010-06-28 21:16:30 +00:00
Bob Wilson
6385cb2386 Support Thumb mode encoding of NEON instructions. 
llvm-svn: 107068
 2010-06-28 21:12:19 +00:00
Jim Grosbach
a0473aa51c minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
llvm-svn: 106988
 2010-06-28 04:27:01 +00:00
Eli Friedman
893ce468be Followup to r106770: actually generate SXTB and SXTH for sign-extensions. 
llvm-svn: 106940
 2010-06-26 04:36:50 +00:00
Bob Wilson
aff7e7c1cc Add support for encoding NEON VMOV (from scalar to core register) instructions. 
llvm-svn: 106938
 2010-06-26 04:07:15 +00:00
Evan Cheng
f222c09b61 It's now possible to run code placement pass for ARM. 
llvm-svn: 106935
 2010-06-26 01:52:05 +00:00
Bob Wilson
a3b10d15f2 Renumber NEON instruction formats to be consecutive. 
llvm-svn: 106927
 2010-06-26 00:05:09 +00:00
Bob Wilson
b8eaf1ed72 Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to 
"N..." instead of "NEON..." for consistency with the other NEON format names.

llvm-svn: 106921
 2010-06-25 23:56:05 +00:00
Bob Wilson
3ace799cfe Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. 
Renumber MiscFrm to 25.

llvm-svn: 106916
 2010-06-25 23:45:37 +00:00
Daniel Dunbar
c0c37cea64 Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was 
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

llvm-svn: 106908
 2010-06-25 23:14:54 +00:00
Evan Cheng
346aecdb8b Change if-conversion block size limit checks to add some flexibility. 
llvm-svn: 106901
 2010-06-25 22:42:03 +00:00
Bob Wilson
d1e4e67954 Add support for encoding 3-register NEON instructions, and fix 
emitNEON2RegInstruction's handling of 2-address operands.

llvm-svn: 106900
 2010-06-25 22:40:46 +00:00
Dale Johannesen
b1fc776fca The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

llvm-svn: 106893
 2010-06-25 21:55:36 +00:00
Bob Wilson
a1739048a1 Add support for encoding 2-register NEON instructions. 
llvm-svn: 106891
 2010-06-25 21:17:19 +00:00
Bob Wilson
4d54e03068 Fix indentation. 
llvm-svn: 106881
 2010-06-25 20:54:44 +00:00