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246 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky
336c64c5d0 [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x 
See bug 36835: https://bugs.llvm.org/show_bug.cgi?id=36835

Differential Revision: https://reviews.llvm.org/D44825

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328707
 2018-03-28 14:53:13 +00:00
Dmitry Preobrazhensky
585626cbac [AMDGPU][MC][GFX9] Added s_scratch* instructions 
See bug 36836: https://bugs.llvm.org/show_bug.cgi?id=36836

Differential Revision: https://reviews.llvm.org/D44832

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328704
 2018-03-28 14:08:03 +00:00
Tim Corringham
6c9d475041 [AMDGPU] Improve disassembler error handling 
Summary:
llvm-objdump now disassembles unrecognised opcodes as data, using
the .long directive. We treat unrecognised opcodes as being 32 bit
values, so move along 4 bytes rather than the single byte which
previously resulted in a cascade of bogus disassembly following an
unrecognised opcode.

While no solution can always disassemble code that contains
embedded data correctly this provides a significant improvement.

The disassembler will now cope with an arbitrary length section
as it no longer truncates it to a multiple of 4 bytes, and will
use the .byte directive for trailing bytes.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D44685

llvm-svn: 328553
 2018-03-26 17:06:33 +00:00
Dmitry Preobrazhensky
dcb1f31f28 [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes 
See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751

Differential Revision: https://reviews.llvm.org/D44529

Reviewers: artem.tamazov, arsenm
llvm-svn: 327723
 2018-03-16 16:38:04 +00:00
Dmitry Preobrazhensky
def59269c9 [AMDGPU][MC] Corrected default values for unused SDWA operands 
See bug 36355:  https://bugs.llvm.org/show_bug.cgi?id=36355

Differential Revision: https://reviews.llvm.org/D44481

Reviewers: artem.tamazov, arsenm
llvm-svn: 327720
 2018-03-16 15:40:27 +00:00
Dmitry Preobrazhensky
d45a36011a [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction 
See bug 36558: https://bugs.llvm.org/show_bug.cgi?id=36558

Differential Revision: https://reviews.llvm.org/D43950

Reviewers: artem.tamazov, arsenm
llvm-svn: 327299
 2018-03-12 17:29:24 +00:00
Dmitry Preobrazhensky
ec04f22e77 [AMDGPU][MC] Corrected GATHER4 opcodes 
See bug 36252: https://bugs.llvm.org/show_bug.cgi?id=36252

Differential Revision: https://reviews.llvm.org/D43874

Reviewers: artem.tamazov, arsenm
llvm-svn: 327278
 2018-03-12 15:03:34 +00:00
Stanislav Mekhanoshin
f419b798c5 [AMDGPU] Add default ISA version targets 
In case if -mattr used to modify feature set bits in llvm-mc call
getIsaVersion can fail to identify specific ISA due to test mismatch.
Adding default fallback tests which will always correctly report at
least major version.

Differential Revision: https://reviews.llvm.org/D44163

llvm-svn: 326825
 2018-03-06 18:33:55 +00:00
Dmitry Preobrazhensky
a6d039d869 [AMDGPU][MC] Added lds support for MUBUF instructions 
See bug 28234: https://bugs.llvm.org/show_bug.cgi?id=28234

Differential Revision: https://reviews.llvm.org/D43472

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 325676
 2018-02-21 13:13:48 +00:00
Konstantin Zhuravlyov
bffa850abe AMDGPU: Bring processors and features in sync with the spec 
- Remove gfx800
- Make iceland gfx802
- Add xnack to gfx902

Differential Revision: https://reviews.llvm.org/D43355

llvm-svn: 325393
 2018-02-16 21:26:25 +00:00
Dmitry Preobrazhensky
e8a7910a4d [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier 
See bug 36154: https://bugs.llvm.org/show_bug.cgi?id=36154

Differential Revision: https://reviews.llvm.org/D42847

Reviewers: cfang, artem.tamazov, arsenm
llvm-svn: 324237
 2018-02-05 14:18:53 +00:00
Dmitry Preobrazhensky
1c461e7122 [AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes 
See bugs 36094, 36095:
  https://bugs.llvm.org/show_bug.cgi?id=36094
  https://bugs.llvm.org/show_bug.cgi?id=36095

Differential Revision: https://reviews.llvm.org/D42692

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 324231
 2018-02-05 12:45:43 +00:00
Dmitry Preobrazhensky
ce6c21d753 [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16 
See bugs 36092, 36093:
    https://bugs.llvm.org/show_bug.cgi?id=36092
    https://bugs.llvm.org/show_bug.cgi?id=36093

Differential Revision: https://reviews.llvm.org/D42583

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323651
 2018-01-29 14:20:42 +00:00
Dmitry Preobrazhensky
72ddafbbfa [AMDGPU][MC] Added validation of image dst/data size (must match dmask and tfe) 
See bug 36000: https://bugs.llvm.org/show_bug.cgi?id=36000

Differential Revision: https://reviews.llvm.org/D42483

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323538
 2018-01-26 16:42:51 +00:00
Dmitry Preobrazhensky
303c310c6e [AMDGPU][MC] Added support of 64-bit image atomics 
See bug 35998: https://bugs.llvm.org/show_bug.cgi?id=35998

Differential Revision: https://reviews.llvm.org/D42469

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323534
 2018-01-26 15:43:29 +00:00
Dmitry Preobrazhensky
23c831adb2 [AMDGPU][MC] Corrected parsing of image modifiers and encoding of image atomics 
See bugs
    35962: https://bugs.llvm.org/show_bug.cgi?id=35962
    35963: https://bugs.llvm.org/show_bug.cgi?id=35963

Differential Revision: https://reviews.llvm.org/D42184

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322942
 2018-01-19 13:49:53 +00:00
Dmitry Preobrazhensky
fda42c21ab [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands 
See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771

Differential Revision: https://reviews.llvm.org/D42058

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322655
 2018-01-17 14:00:48 +00:00
Stanislav Mekhanoshin
b2de8bbb4a [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32 
Differential Revision: https://reviews.llvm.org/D41617

llvm-svn: 322500
 2018-01-15 18:49:15 +00:00
Changpeng Fang
14b06e6060 AMDGPU/SI: Add d16 support for buffer intrinsics. 
Differential Revision:
  https://reviews.llvm.org/D38906

Reviewers:
  Matt and Brian.

llvm-svn: 322402
 2018-01-12 21:12:19 +00:00
Dmitry Preobrazhensky
01bdb0ae28 [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 
See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764

Differential Revision: https://reviews.llvm.org/D41614

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322189
 2018-01-10 14:22:19 +00:00
Dmitry Preobrazhensky
d5688de246 [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers 
See bug 35730: https://bugs.llvm.org/show_bug.cgi?id=35730

Differential Revision: https://reviews.llvm.org/D41598

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 321552
 2017-12-29 13:55:11 +00:00
Dmitry Preobrazhensky
db06df90f8 [AMDGPU][MC] Corrected handling of negative expressions 
See bug 35716: https://bugs.llvm.org/show_bug.cgi?id=35716

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41488

llvm-svn: 321372
 2017-12-22 18:03:35 +00:00
Dmitry Preobrazhensky
e80d391b33 [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32 
See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41186

llvm-svn: 321367
 2017-12-22 17:13:28 +00:00
Dmitry Preobrazhensky
b8925d0036 [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers 
See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561

This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic.

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41437

llvm-svn: 321359
 2017-12-22 15:18:06 +00:00
Matt Arsenault
c6e25cd04d [AMDGPU, AsmParser] Enable the mnemonic spell corrector. 
Patch by Dmitry Venikov

llvm-svn: 321202
 2017-12-20 18:52:57 +00:00
Dmitry Preobrazhensky
6baa8ed1f1 [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma 
See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41007

llvm-svn: 320375
 2017-12-11 15:23:20 +00:00
Konstantin Zhuravlyov
9b3981c8d5 AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 
- Add gfx704
    - Change bonaire to gfx704
  - Remove gfx804
  - Remove gfx901
  - Remove gfx903

Differential Revision: https://reviews.llvm.org/D40046

llvm-svn: 320194
 2017-12-08 20:52:28 +00:00
Konstantin Zhuravlyov
ec13d639b3 AMDGPU: Add num spilled s/vgprs to metadata 
This was requested by tools.

Differential Revision: https://reviews.llvm.org/D40321

llvm-svn: 319192
 2017-11-28 17:51:08 +00:00
Dmitry Preobrazhensky
77393a5f25 [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16 
See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Reviewers: artem.tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D39488

llvm-svn: 318955
 2017-11-24 15:37:14 +00:00
Dmitry Preobrazhensky
7cd493f906 [AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility with SP3 
See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329

Reviewers: arsenm, vpykhtin, artem.tamazov

Differential Revision: https://reviews.llvm.org/D40350

llvm-svn: 318947
 2017-11-24 13:22:38 +00:00
Dmitry Preobrazhensky
195b0670d3 [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9 
Summary:
Added tests to better cover features introduced by commit rL318675.
See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675

llvm-svn: 318841
 2017-11-22 15:47:27 +00:00
Dmitry Preobrazhensky
551dde9f3b [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 
See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765

Reviewers: tamazov, SamWot, arsenm, vpykhtin

Differential Revision: https://reviews.llvm.org/D40088

llvm-svn: 318675
 2017-11-20 18:24:21 +00:00
Dmitry Preobrazhensky
6d12a70c62 [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix* 
See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148

Reviewers: tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D39492

llvm-svn: 318526
 2017-11-17 15:15:40 +00:00
Konstantin Zhuravlyov
762f1d9a9a AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistency 
Differential Revision: https://reviews.llvm.org/D38957

llvm-svn: 316097
 2017-10-18 17:31:09 +00:00
Konstantin Zhuravlyov
9e40a87f50 AMDGPU: Start generating metadata for MaxFlatWorkGroupSize 
Differential Revision: https://reviews.llvm.org/D38958

llvm-svn: 316024
 2017-10-17 20:03:21 +00:00
Konstantin Zhuravlyov
d68ff516d3 AMDGPU: Bring HSA metadata on par with the specification 
Differential Revision: https://reviews.llvm.org/D38753

llvm-svn: 315821
 2017-10-14 19:03:51 +00:00
Konstantin Zhuravlyov
fd75ed74e2 AMDGPU: Improve note directive verification in assembler 
- Do not allow amd_amdgpu_isa directives on non-amdgcn architectures
  - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes
  - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes

Differential Revision: https://reviews.llvm.org/D38750

llvm-svn: 315812
 2017-10-14 16:15:28 +00:00
Konstantin Zhuravlyov
c9bc3fd2a9 AMDGPU: Do not emit deprecated notes for code object v3 
Differential Revision: https://reviews.llvm.org/D38749

llvm-svn: 315810
 2017-10-14 15:59:07 +00:00
Konstantin Zhuravlyov
7f60cf2fb0 AMDGPU: Add support for isa version note 
- Emit NT_AMD_AMDGPU_ISA
  - Add assembler parsing for isa version directive
    - If isa version directive does not match command line arguments, then return error

Differential Revision: https://reviews.llvm.org/D38748

llvm-svn: 315808
 2017-10-14 15:40:33 +00:00
Konstantin Zhuravlyov
3703817c5c AMDGPU/NFC: Minor clean ups in PAL metadata 
- Move PAL metadata definitions to AMDGPUMetadata
  - Make naming consistent with HSA metadata

Differential Revision: https://reviews.llvm.org/D38745

llvm-svn: 315523
 2017-10-11 22:41:09 +00:00
Konstantin Zhuravlyov
bea150402f AMDGPU/NFC: Rename code object metadata as HSA metadata 
- Rename AMDGPUCodeObjectMetadata to AMDGPUMetadata (PAL metadata will be included in this file in the follow up change)
  - Rename AMDGPUCodeObjectMetadataStreamer to AMDGPUHSAMetadataStreamer
  - Introduce HSAMD namespace
  - Other minor name changes in function and test names

llvm-svn: 315522
 2017-10-11 22:18:53 +00:00
Tim Renouf
f4680f0891 [AMDGPU] implemented pal metadata 
Summary:
For the amdpal OS type:

We write an AMDGPU_PAL_METADATA record in the .note section in the ELF
(or as an assembler directive). It contains key=value pairs of 32 bit
ints. It is a merge of metadata from codegen of the shaders, and
metadata provided by the frontend as _amdgpu_pal_metadata IR metadata.
Where both sources have a key=value with the same key, the two values
are ORed together.

This .note record is part of the amdpal ABI and will be documented in
docs/AMDGPUUsage.rst in a future commit.

Eventually the amdpal OS type will stop generating the .AMDGPU.config
section once the frontend has safely moved over to using the .note
records above instead of .AMDGPU.config.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D37753

llvm-svn: 314829
 2017-10-03 19:03:52 +00:00
Nicolai Haehnle
e0ed17495b AMDGPU: fix bad test exposed by r314522 
The test attempts to use -1 as carry-in for v_addc_*.

Before writing r314522, I did actually test this on real hardware,
and found that it doesn't work. So r314522 is correct in restricting
the carry-in operand: just remove those tests to make things pass
again.

llvm-svn: 314530
 2017-09-29 16:07:05 +00:00
Matt Arsenault
d1934c5240 AMDGPU: Fix encoding of op_sel for mad_mix* opcodes 
llvm-svn: 313797
 2017-09-20 19:09:28 +00:00
Matt Arsenault
960a469e7e AMDGPU: Add ds_{read|write}_addtid_b32 definitions 
llvm-svn: 312349
 2017-09-01 18:38:02 +00:00
Matt Arsenault
d48237c09b AMDGPU: Add most d16 load/store instruction definitions 
Doesn't include the tied operand necessary for the loads,
but is enough for the assembler to work.

llvm-svn: 312347
 2017-09-01 18:36:06 +00:00
Matt Arsenault
de478ba30e AMDGPU: Correct operand types for v_mad_mix* 
These aren't really packed instructions, so the default
op_sel_hi should be 0 since this indicates a conversion.
The operand types are scalar values that behave similar
to an f16 scalar that may be converted to f32.

Doesn't change the default printing for op_sel_hi, just
the parsing.

llvm-svn: 312179
 2017-08-30 22:18:40 +00:00
Dmitry Preobrazhensky
5a0fe39d12 [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16 
This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36694

llvm-svn: 311011
 2017-08-16 15:16:32 +00:00
Dmitry Preobrazhensky
be2eb2d0a8 [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes 
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36674

llvm-svn: 311006
 2017-08-16 13:51:56 +00:00
Dmitry Preobrazhensky
559a664ace [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes 
See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Reviewers: vpykhtin, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D36322

llvm-svn: 310497
 2017-08-09 17:10:47 +00:00