1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-25 05:52:53 +02:00
Commit Graph

24 Commits

Author SHA1 Message Date
Evan Cheng
6e799c3c58 Cmp peephole optimization isn't always safe for signed arithmetics.
int tries = INT_MAX;    
while (tries > 0) {
      tries--;
}

The check should be:
        subs    r4, #1
        cmp     r4, #0
        bgt     LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742

llvm-svn: 128179
2011-03-23 22:52:04 +00:00
Jim Grosbach
1986d9ac8f Properly pseudo-ize MOVCCr and MOVCCs.
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Bill Wendling
4340c9449a When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
2010-11-01 20:41:43 +00:00
Bill Wendling
a59bb03780 More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905
2010-11-01 05:59:43 +00:00
Jim Grosbach
804505c7d4 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
2010-10-14 22:57:13 +00:00
Jim Grosbach
29dc23398f Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.

llvm-svn: 116512
2010-10-14 20:43:44 +00:00
Jim Grosbach
d2cf0742a4 Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.

llvm-svn: 114221
2010-09-17 21:58:46 +00:00
Bill Wendling
8c5ac0d30c Update test to match output of optimize compares for ARM.
llvm-svn: 110765
2010-08-11 01:05:02 +00:00
Dan Gohman
0be71f4660 Teach EmitLiveInCopies to omit copies for unused virtual registers,
and to clean up unused incoming physregs from the live-in list.

llvm-svn: 106805
2010-06-24 22:23:02 +00:00
Evan Cheng
5541068ad3 Run codegen dce pass for all targets at all optimization levels. Previously it's
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493
2010-02-06 09:07:11 +00:00
Jim Grosbach
2a445e5d0a Update test to be more explicit about what instruction sequences are expected for each operation.
llvm-svn: 85689
2009-10-31 21:52:58 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline
llvm-svn: 85687
2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline
llvm-svn: 85685
2009-10-31 21:00:56 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
2009-10-31 19:38:01 +00:00
Benjamin Kramer
60dac7de40 Add missing colons for FileCheck.
llvm-svn: 85674
2009-10-31 19:22:24 +00:00
Jim Grosbach
78a5bcfa02 Convert to FileCheck
llvm-svn: 85673
2009-10-31 19:06:53 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
Evan Cheng
b4139189b0 Move thumb and thumb2 tests into separate directories.
llvm-svn: 74068
2009-06-24 06:36:07 +00:00
Dan Gohman
794fa1f8f7 Convert tests using "| wc -l | grep ..." to use the count script.
llvm-svn: 41097
2007-08-15 13:36:28 +00:00
Reid Spencer
df17fa8ef9 For PR1319:
Remove && from the end of the lines to prevent tests from throwing run
lines into the background. Also, clean up places where the same command
is run multiple times by using a temporary file.

llvm-svn: 36142
2007-04-16 17:36:08 +00:00
Evan Cheng
5d49a6be02 -march=arm -enable-thumb => -march=thumb
llvm-svn: 34522
2007-02-23 03:15:39 +00:00
Reid Spencer
591bfa1e0b Changes to support making the shift instructions be true BinaryOperators.
This feature is needed in order to support shifts of more than 255 bits
on large integer types.  This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
   shl i32 %X, 1
instead of
   shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.

llvm-svn: 33776
2007-02-02 02:16:23 +00:00
Evan Cheng
ffed2abf43 Merge tests.
llvm-svn: 33560
2007-01-27 00:04:57 +00:00
Evan Cheng
1897bbd2cf ARM test cases contributed by Apple.
llvm-svn: 33354
2007-01-19 09:20:23 +00:00