The JIT is designed to code-generate a function at-a-time. That means that any
pass can only make local changes to its function. Period.
Because the Sparc PreSelection pass claims to be a BasicBlock pass while adding
globals to the Module, it cannot be run with the other passes, because by this
time, the globals have been output already by the JIT, and the addresses of any
globals appearing AFTER this point are not recognized.
However, the PreSelection pass is a requirement for correctness in the Sparc
codegen path, so it MUST be run.
::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::
llvm-svn: 6650
This avoid generating a register to hold C, which in turn speeds up the
register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2. This
also speeds up other passes. This also speeds up execution of the program
marginally, and makes the asm much easier to read. :)
llvm-svn: 6626
Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.
llvm-svn: 6619
Update file comment to contain a bunch of the overview mapping-info
documentation previously buried within the file.
Remove some unnecessary include/using stmts.
Rename pass to MappingInfoCollector.
Rewrite a lot of it so it doesn't use global instance variables and so
it outputs into MappingInfo objects and then dumps those out, instead of going
straight to an assembly file.
Change name of factory to getMappingInfoCollector.
Fold prologue & epilogue writers into MappingInfo methods.
lib/Target/Sparc/FInfo.cpp:
Correct file comment to reflect above change
lib/Target/Sparc/Sparc.cpp:
Change name of factory to getMappingInfoCollector.
llvm-svn: 6617
in Emitter.cpp, just convert the Sparc version of the constant pool into
what's already supported and inter-operate.
* Implemented a first pass at lazy function resolution in the JITResolver. That
required adding a SparcV9CodeEmitter pointer to simplify generating
bit-patterns of the instructions.
* SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes
sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and
lives for the entire duration of the JIT (via PassManager which lives in VM).
* Changed all return values in the JITResolver to uint64_t because of the 64-bit
Sparc architecture.
* Added a new version of getting the value of a GlobalValue in the
SparcV9CodeEmitter, which now works for already-generated functions (JITted or
library functions).
* Removed little-used and unused functions, cleaning up the internal view of the
SparcV9CodeEmitter.
llvm-svn: 6612
laid out closer to the VM so that calls to library functions (e.g. puts()) and
callback (e.g. JITResolver::CompilationCallback) fit into 30 bits of the call
instruction.
* Abort if architecture is not yet supported (not X86 or Sparc) because it
likely requires a different set of parameters to mmap() .
* Stop using hard-coded values for page size; use sysconf(_SC_PAGESIZE) instead.
llvm-svn: 6610
the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.
llvm-svn: 6602
rewriting it. I also vacuumed out all the commented-out code and
inaccurate comments, etc.
(We need to put the mapping information in a data structure so that we can
pass it out to the JIT, instead of automagically converting it to .byte
directives.)
llvm-svn: 6574
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
llvm-svn: 6564
* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .
llvm-svn: 6561
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).
llvm-svn: 6560
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
llvm-svn: 6548
* No more createX86Emitter() vs. createSparcEmitter() -- there can be only one
* As a result, the memory management semantics must be handled according to
platform -- the parameters to mmap() are particularly sensitive to the host
architecture.
llvm-svn: 6527
TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.
llvm-svn: 6469
preallocated. While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.
llvm-svn: 6467
globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.
llvm-svn: 6466
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.
Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.
The other changes are just elimination of unnecessary spaces.
llvm-svn: 6437
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
their fields were totally screwed up. This seems to fix the problem.
llvm-svn: 6429
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.
Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.
llvm-svn: 6392
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
llvm-svn: 6384
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.
llvm-svn: 6376
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.
This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.
llvm-svn: 6375
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.
This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.
As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.
llvm-svn: 6371
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes
llvm-svn: 6369
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.
llvm-svn: 6366
`lli -march=x86' or `lli -march=sparc' will forcefully select the JIT even on a
different platform. Running lli without the -march option will select the JIT
for the platform that it's currently running on.
Pro: can test Sparc JIT (debug printing mode) on X86 -- faster to compile/link
LLVM source base to test changes.
Con: Linking lli on x86 now pulls in all the Sparc libs -> longer link time
(but X86 can bear it, right?)
In the future, perhaps this should be a ./configure option to enable/disable
target JITting...
llvm-svn: 6360
that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).
Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .
llvm-svn: 6357
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
llvm-svn: 6341
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339
This was a problem with constants having their types resolved to some new type,
but there was already a constant of the new type created. Before, these types
were never merged together, now they are.
llvm-svn: 6314
function and no symbols were explicitly marked to be externalized.
* Add new -internalize-public-api-list option that can be used if the symbol
list is small, and making a new file is annoying.
llvm-svn: 6289
