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Author SHA1 Message Date
Nate Begeman
3b1c0df702 Next round of PPC CR optimizations. For the following code: 
int %bar(float %a, float %b, float %c, float %d) {
entry:
    %tmp.1 = setlt float %a, %d
    %tmp.2 = setlt float %b, %d
    %or = or bool %tmp.1, %tmp.2
    %tmp.3 = setgt float %c, %d
    %tmp.4 = or bool %or, %tmp.3
    %tmp.5 = and bool %tmp.4, true
    %retval = cast bool %tmp.5 to int
    ret int %retval
}

We now emit:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr0, f1, f4
        fcmpu cr1, f2, f4
        cror 0, 0, 4
        fcmpu cr1, f3, f4
        cror 28, 0, 5
        mfcr r2
        rlwinm r3, r2, 29, 31, 31
        blr

Instead of:

_bar:
.LBB_bar_0:     ; entry
        fcmpu cr7, f1, f4
        mfcr r2
        rlwinm r2, r2, 29, 31, 31
        fcmpu cr7, f2, f4
        mfcr r3
        rlwinm r3, r3, 29, 31, 31
        or r2, r2, r3
        fcmpu cr7, f3, f4
        mfcr r3
        rlwinm r3, r3, 30, 31, 31
        or r3, r2, r3
        blr

llvm-svn: 21321
 2005-04-18 07:48:09 +00:00
Chris Lattner
4d9c1d06da silence a bogus warning 
llvm-svn: 21320
 2005-04-18 05:26:21 +00:00
Chris Lattner
188ecaab1d Fold setcc of MVT::i1 operands into logical operations 
llvm-svn: 21319
 2005-04-18 04:48:12 +00:00
Chris Lattner
72aca1b758 Another minor simplification: handle setcc (zero_extend x), c -> setcc(x, c') 
llvm-svn: 21318
 2005-04-18 04:30:45 +00:00
Chris Lattner
e6117e5d4f Another simple xform 
llvm-svn: 21317
 2005-04-18 04:11:19 +00:00
Chris Lattner
f6f5b23a00 Fold: 
// (X != 0) | (Y != 0) -> (X|Y != 0)
        // (X == 0) & (Y == 0) -> (X|Y == 0)

Compiling this:

int %bar(int %a, int %b) {
        entry:
        %tmp.1 = setne int %a, 0
        %tmp.2 = setne int %b, 0
        %tmp.3 = or bool %tmp.1, %tmp.2
        %retval = cast bool %tmp.3 to int
        ret int %retval
        }

to this:

_bar:
        or r2, r3, r4
        addic r3, r2, -1
        subfe r3, r3, r2
        blr

instead of:

_bar:
        addic r2, r3, -1
        subfe r2, r2, r3
        addic r3, r4, -1
        subfe r3, r3, r4
        or r3, r2, r3
        blr

llvm-svn: 21316
 2005-04-18 03:59:53 +00:00
Chris Lattner
a32c50520c Make the AND elimination operation recursive and significantly more powerful, 
eliminating an and for Nate's testcase:

int %bar(int %a, int %b) {
        entry:
        %tmp.1 = setne int %a, 0
        %tmp.2 = setne int %b, 0
        %tmp.3 = or bool %tmp.1, %tmp.2
        %retval = cast bool %tmp.3 to int
        ret int %retval
        }

generating:

_bar:
        addic r2, r3, -1
        subfe r2, r2, r3
        addic r3, r4, -1
        subfe r3, r3, r4
        or r3, r2, r3
        blr

instead of:

_bar:
        addic r2, r3, -1
        subfe r2, r2, r3
        addic r3, r4, -1
        subfe r3, r3, r4
        or r2, r2, r3
        rlwinm r3, r2, 0, 31, 31
        blr

llvm-svn: 21315
 2005-04-18 03:48:41 +00:00
Nate Begeman
85cd65b389 Change codegen for setcc to read the bit directly out of the condition 
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314
 2005-04-18 02:43:24 +00:00
Chris Lattner
25a77fc58f Add support for targets that require stubs for external functions. 
llvm-svn: 21313
 2005-04-18 01:44:27 +00:00
Chris Lattner
a1fd64a073 Handle ExternalSymbol operands in the PPC JIT 
llvm-svn: 21312
 2005-04-18 00:46:10 +00:00
Nate Begeman
e82d5edfee Update dejagnu tests to use the new pattern isel flag 
llvm-svn: 21311
 2005-04-16 04:25:48 +00:00
Jeff Cohen
80e7b74819 Add CondPropagate.cpp to VC++ Transforms project 
llvm-svn: 21310
 2005-04-16 02:51:44 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
 2005-04-15 22:12:16 +00:00
Chris Lattner
8456833fa8 new pass 
llvm-svn: 21307
 2005-04-15 21:13:16 +00:00
Chris Lattner
a117cf4215 a new simple pass, which will be extended to be more useful in the future. 
This pass forward branches through conditions when it can show that the
conditions is either always true or false for a predecessor.  This currently
only handles the most simple cases of this, but is successful at threading
across 2489 branches and 65 switch instructions in 176.gcc, which isn't bad.

llvm-svn: 21306
 2005-04-15 19:28:32 +00:00
Chris Lattner
ca287099e1 add a new prototype 
llvm-svn: 21305
 2005-04-15 19:24:49 +00:00
Chris Lattner
6e6776322d new testcase 
llvm-svn: 21304
 2005-04-15 19:24:36 +00:00
Andrew Lenharth
f091300df2 fix calls 
llvm-svn: 21303
 2005-04-14 17:34:20 +00:00
Andrew Lenharth
23a5d0bba4 a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases 
llvm-svn: 21302
 2005-04-14 16:24:00 +00:00
Andrew Lenharth
41c4b9c268 added a random and mask test 
llvm-svn: 21301
 2005-04-14 16:17:49 +00:00
Duraid Madina
0c40c548c0 print negative 64 bit immediates as negative numbers, makes things a little 
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything

llvm-svn: 21300
 2005-04-14 10:08:01 +00:00
Duraid Madina
b8dfae92e9 oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4 
llvm-svn: 21299
 2005-04-14 10:06:35 +00:00
Nate Begeman
604895b03c Implement multi-way branches through logical ops on condition registers. 
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
 2005-04-14 09:45:08 +00:00
Nate Begeman
ce63e383b8 Add a couple missing transforms in getSetCC that were triggering assertions 
in the PPC Pattern ISel

llvm-svn: 21297
 2005-04-14 08:56:52 +00:00
Duraid Madina
eb4c15b42c we have zextloads, not sextloads! 
llvm-svn: 21296
 2005-04-14 08:37:32 +00:00
Nate Begeman
b707ec16b4 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
 2005-04-14 03:20:38 +00:00
Nate Begeman
99a9840b56 Start allocating condition registers. Almost all explicit uses of CR0 are 
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294
 2005-04-13 23:15:44 +00:00
Nate Begeman
ae49d52006 Implement the fold shift X, zext(Y) -> shift X, Y at the target level, 
where it is safe to do so.

llvm-svn: 21293
 2005-04-13 22:14:14 +00:00
Nate Begeman
33b835c553 Add CodeGen tests for the recent SelectionDAG transforms 
llvm-svn: 21292
 2005-04-13 21:45:13 +00:00
Nate Begeman
20b3399465 Disbale the broken fold of shift + sz[ext] for now 
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291
 2005-04-13 21:23:31 +00:00
Chris Lattner
89f7e115a4 fix an infinite loop 
llvm-svn: 21289
 2005-04-13 20:06:29 +00:00
Chris Lattner
475fe85ddf fix some serious miscompiles on ia64, alpha, and ppc 
llvm-svn: 21288
 2005-04-13 19:53:40 +00:00
Chris Lattner
03d675414e avoid work when possible, perhaps fix the problem nate and andrew are seeing 
with != 0 comparisons vanishing.

llvm-svn: 21287
 2005-04-13 19:41:05 +00:00
Andrew Lenharth
cbf7a52768 WOW, function calls still seem to work after this. 
llvm-svn: 21286
 2005-04-13 17:17:28 +00:00
Andrew Lenharth
d1fee6d24a prepare for func call optimization 
llvm-svn: 21285
 2005-04-13 16:19:50 +00:00
Andrew Lenharth
69541f896f regression case for faster call sequence 
llvm-svn: 21284
 2005-04-13 16:16:01 +00:00
Andrew Lenharth
18f93d4455 check that casts still use zap 
llvm-svn: 21283
 2005-04-13 13:00:16 +00:00
Duraid Madina
b9d2d9ac63 * add the shladd instruction 
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
 2005-04-13 06:12:04 +00:00
Andrew Lenharth
ec33ab6a2f add matches for SxADDL and company, as well as simplify the SxADDQ code 
llvm-svn: 21281
 2005-04-13 05:19:55 +00:00
Chris Lattner
9540cf8c7e Implement expansion of unsigned i64 -> FP. 
Note that this probably only works for little endian targets, but is enough
to get siod working :)

llvm-svn: 21280
 2005-04-13 05:09:42 +00:00
Duraid Madina
67e553e521 * if ANDing with a constant of the form: 
0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279
 2005-04-13 04:50:54 +00:00
Andrew Lenharth
9be54f8a6a added s4addl matching test 
llvm-svn: 21277
 2005-04-13 04:41:06 +00:00
Andrew Lenharth
510db15268 added all flavors of zap for anding 
llvm-svn: 21276
 2005-04-13 03:47:03 +00:00
Chris Lattner
1a6247ff51 Make expansion of uint->fp cast assert out instead of infinitely recurse. 
llvm-svn: 21275
 2005-04-13 03:42:14 +00:00
Chris Lattner
85c6a7bed0 Fix some mysteriously missing {}'s which cause the miscompilation of 
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
 2005-04-13 03:29:53 +00:00
Chris Lattner
63450e87d9 add back the optimization that Nate added for shl X, (zext_inreg y) 
llvm-svn: 21273
 2005-04-13 02:58:13 +00:00
Chris Lattner
759afe07d7 Oops, remove these too. 
llvm-svn: 21272
 2005-04-13 02:47:57 +00:00
Chris Lattner
8489ac991d remove one more occurance of this that snuck in 
llvm-svn: 21271
 2005-04-13 02:46:17 +00:00
Chris Lattner
5fdb103328 Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff 
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270
 2005-04-13 02:43:40 +00:00
Chris Lattner
a2e92e69da Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing 
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269
 2005-04-13 02:41:52 +00:00