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Commit Graph

61114 Commits

Author SHA1 Message Date
Jyotsna Verma
5307666fe8 Reverting r181331.
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt.

llvm-svn: 181334
2013-05-07 17:12:35 +00:00
Jyotsna Verma
af0c734e1b Hexagon: Fix Small Data support to handle -G 0 correctly.
llvm-svn: 181331
2013-05-07 16:42:15 +00:00
Jyotsna Verma
71c6bf55f2 Hexagon: Set accessSize and addrMode on all load/store instructions.
llvm-svn: 181324
2013-05-07 15:06:29 +00:00
Michael Kuperstein
25056babb2 Re-enable AVX detection on x64 platforms.
llvm-svn: 181313
2013-05-07 14:05:33 +00:00
Richard Sandiford
a9580c775a [SystemZ] Fix InitMCCodeGenInfo call
createSystemZMCCodeGenInfo was not passing the optimization level to
InitMCCodeGenInfo(), so -O0 would be ignored.  Fixes DebugInfo/namespace.ll
after the changes in r181271.

llvm-svn: 181312
2013-05-07 12:56:31 +00:00
Timur Iskhodzhanov
5640405cee Fix the VS2010 build broken by r181271
llvm-svn: 181296
2013-05-07 07:47:47 +00:00
Arnold Schwaighofer
f95f087afb LoopVectorize: getConsecutiveVector must respect signed arithmetic
We were passing an i32 to ConstantInt::get where an i64 was needed and we must
also pass the sign if we pass negatives numbers. The start index passed to
getConsecutiveVector must also be signed.

Should fix PR15882.

llvm-svn: 181286
2013-05-07 04:37:05 +00:00
David Blaikie
b40dfb39c7 DebugInfo: Support imported modules in lexical blocks
llvm-svn: 181271
2013-05-06 23:33:07 +00:00
Tom Stellard
3a335f24af R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
2013-05-06 23:02:19 +00:00
Tom Stellard
57e8e4e921 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181268
2013-05-06 23:02:15 +00:00
Tom Stellard
d2ec929c52 R600/SI: Add intrinsic for texture image loading
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
2013-05-06 23:02:12 +00:00
Tom Stellard
4ed2501894 R600/SI: Add pattern for uint_to_fp
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181266
2013-05-06 23:02:07 +00:00
Tom Stellard
7d53018f9b R600/SI: Add patterns for integer maxima / minima
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181265
2013-05-06 23:02:04 +00:00
Tom Stellard
2c5ed6e6ce R600/SI: Add pattern for AMDGPU.trunc intrinsic
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181263
2013-05-06 23:02:00 +00:00
Krzysztof Parzyszek
b05e065c7b Print IR from Hexagon MI passes with -print-before/after-all.
llvm-svn: 181255
2013-05-06 21:58:00 +00:00
Andrew Trick
66c37e7321 Implemented public interface for modifying registered (not positional or sink options) command line options at runtime.
Patch by Dan Liew!

llvm-svn: 181254
2013-05-06 21:56:35 +00:00
Andrew Trick
7cf2347306 Support command line option categories.
Patch by Dan Liew!

llvm-svn: 181253
2013-05-06 21:56:23 +00:00
Krzysztof Parzyszek
1f0992737e Cleanup of the HexagonTargetMachine setup.
llvm-svn: 181250
2013-05-06 21:25:45 +00:00
David Majnemer
68574fa9e6 InstCombine: (X ^ signbit) + C -> X + (signbit ^ C)
llvm-svn: 181249
2013-05-06 21:21:31 +00:00
Eric Christopher
3cc2bddd41 Hoist boundary condition out of loop header.
llvm-svn: 181248
2013-05-06 21:19:44 +00:00
Eric Christopher
eb2243ca76 Untabify.
llvm-svn: 181247
2013-05-06 21:19:41 +00:00
Jyotsna Verma
0ec07a2dbc Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
llvm-svn: 181235
2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek
afd38d8a5a Make references to HexagonTargetMachine "const".
llvm-svn: 181233
2013-05-06 18:38:37 +00:00
Andrew Trick
5d13ab6ea6 Rotate multi-exit loops even if the latch was simplified.
Test case by Michele Scandale!

Fixes PR10293: Load not hoisted out of loop with multiple exits.

There are few regressions with this patch, now tracked by
rdar:13817079, and a roughly equal number of improvements. The
regressions are almost certainly back luck because LoopRotate has very
little idea of whether rotation is profitable. Doing better requires a
more comprehensive solution.

This checkin is a quick fix that lacks generality (PR10293 has
a counter-example). But it trivially fixes the case in PR10293 without
interfering with other cases, and it does satify the criteria that
LoopRotate is a loop canonicalization pass that should avoid
heuristics and special cases.

I can think of two approaches that would probably be better in
the long run. Ultimately they may both make sense.

(1) LoopRotate should check that the current header would make a good
loop guard, and that the loop does not already has a sufficient
guard. The artifical SimplifiedLoopLatch check would be unnecessary,
and the design would be more general and canonical. Two difficulties:

- We need a strong guarantee that we won't endlessly rotate, so the
  analysis would need to be precise in order to avoid the
  SimplifiedLoopLatch precondition.

- Analysis like this are usually based on SCEV, which we don't want to
  rely on.

(2) Rotate on-demand in late loop passes. This could even be done by
shoving the loop back on the queue after the optimization that needs
it. This could work well when we find LICM opportunities in
multi-branch loops. This requires some work, and it doesn't really
solve the problem of SCEV wanting a loop guard before the analysis.

llvm-svn: 181230
2013-05-06 17:58:18 +00:00
Tom Stellard
740d847e2c R600: Remove dead code from the CodeEmitter v2
v2:
  - Replace switch statement with TSFlags query

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181229
2013-05-06 17:50:57 +00:00
Tom Stellard
fb8e73f3af R600: Emit config values in register / value pairs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
2013-05-06 17:50:51 +00:00
Eric Christopher
c179ac43fa Remove unnecessary instance variable and rework logic accordingly.
llvm-svn: 181227
2013-05-06 17:50:50 +00:00
Eric Christopher
5bf0cdb91a Grammar.
llvm-svn: 181226
2013-05-06 17:50:46 +00:00
Tom Stellard
6c3f6e1b02 R600: Stop emitting the instruction type byte before each instruction
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
2013-05-06 17:50:44 +00:00
Eric Christopher
4cbb105dfc Don't emit .dwo sections unless they exist.
llvm-svn: 181224
2013-05-06 17:50:42 +00:00
Tom Stellard
ebe049fd75 R600: Emit ISA for CALL_FS_* instructions
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
2013-05-06 17:50:26 +00:00
Ulrich Weigand
2d456969d5 [SystemZ] Update non-pic DWARF encodings
As pointed out by Rafael Espindola, we should match the DWARF encodings
produced by GCC in both pic and non-pic modes.  This was not the case
for the non-pic case.

This patch changes all DWARF encodings to DW_EH_PE_absptr for the
non-pic case, just like GCC does.  The test case is updated to check
for both variants.

llvm-svn: 181222
2013-05-06 17:28:30 +00:00
Adhemerval Zanella
3b2874423e PowerPC: Fix unimplemented relocation on ppc64
This patch handles the R_PPC64_REL64 relocation type for powerpc64
for mcjit.

llvm-svn: 181220
2013-05-06 17:21:23 +00:00
Jean-Luc Duprat
5607a72e21 Provide InstCombines for the following 3 cases:
A * (1 - (uitofp i1 C)) -> select C, 0, A
B * (uitofp i1 C) -> select C, B, 0
select C, 0, A + select C, B, 0 -> select C, B, A

These come up in code that has been hand-optimized from a select to a linear blend, 
on platforms where that may have mattered. We want to undo such changes 
with the following transform:
A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B

llvm-svn: 181216
2013-05-06 16:55:50 +00:00
Ulrich Weigand
558cec9d9b [SystemZ] Add back end
This adds the actual lib/Target/SystemZ target files necessary to
implement the SystemZ target.  Note that at this point, the target
cannot yet be built since the configure bits are missing.  Those
will be provided shortly by a follow-on patch.

This version of the patch incorporates feedback from reviews by
Chris Lattner and Anton Korobeynikov.  Thanks to all reviewers!

Patch by Richard Sandiford.

llvm-svn: 181203
2013-05-06 16:15:19 +00:00
Ulrich Weigand
5d91c7d3fb [SystemZ] Define DWARF encoding
This is another patch in preparation for adding the SystemZ target.
It defines the appropriate values for DWARF encodings; the intent
is to be compatible with what GCC currently does on the target.

Patch by Richard Sandiford.

llvm-svn: 181201
2013-05-06 16:11:12 +00:00
Ulrich Weigand
d9194d871d [PowerPC] Fix memory corruption in AsmParser
As pointed out by Evgeniy Stepanov, assigning a std::string temporary
to a StringRef is not a good idea.  Rework MatchRegisterName to avoid
using the .lower routine.

llvm-svn: 181192
2013-05-06 11:16:57 +00:00
Michael Kuperstein
74685eff73 Fix slightly too aggressive conact_vector optimization.
(Would sometimes optimize away conacts used to extend a vector with undef values)

llvm-svn: 181186
2013-05-06 08:06:13 +00:00
Nadav Rotem
9119c025de Update the comment to mention that we use TTI.
llvm-svn: 181178
2013-05-06 03:06:36 +00:00
Nadav Rotem
8564ccca8b Revert r164763 because it introduces new shuffles.
Thanks Nick Lewycky for pointing this out.

llvm-svn: 181177
2013-05-06 02:39:09 +00:00
Matt Arsenault
34e1805cd0 Fix unchecked uses of DominatorTree in MemoryDependenceAnalysis.
Use unknown results for places where it would be needed

llvm-svn: 181176
2013-05-06 02:07:24 +00:00
Rafael Espindola
15a39ed0e8 Fix const merging when an alias of a const is llvm.used.
We used to disable constant merging not only if a constant is llvm.used, but
also if an alias of a constant is llvm.used. This change fixes that.

llvm-svn: 181175
2013-05-06 01:48:55 +00:00
Rafael Espindola
297c5a1e10 Add EH support to the MCJIT.
This gets exception handling working on ELF and Macho (x86-64 at least).
Other than the EH frame registration, this patch also implements support
for GOT relocations which are used to locate the personality function on
MachO.

llvm-svn: 181167
2013-05-05 20:43:10 +00:00
Evan Cheng
4d42f5b1d5 ARM AnalyzeBranch should conservatively return true when it sees a predicated
indirect branch at the end of the BB. Otherwise if-converter, branch folding
pass may incorrectly update its successor info if it consider BB as fallthrough
to the next BB.

rdar://13782395

llvm-svn: 181161
2013-05-05 18:06:32 +00:00
Evan Cheng
2ebed7706f Teach if-converter to avoid removing BBs whose addresses are takne. rdar://13782395
llvm-svn: 181160
2013-05-05 18:03:49 +00:00
Benjamin Kramer
06f30fc527 LoopVectorize: Print values instead of pointers in debug output.
llvm-svn: 181157
2013-05-05 14:54:52 +00:00
Richard Osborne
816f899c45 [XCore] Add LDAPB instructions.
With the change the disassembler now supports the XCore ISA in its
entirety.

llvm-svn: 181155
2013-05-05 13:36:53 +00:00
Richard Osborne
f5ff5a7e6f [XCore] Update LDAP to use pcrel_imm.
llvm-svn: 181154
2013-05-05 13:33:10 +00:00
Richard Osborne
0777489aca [XCore] Rename calltarget -> pcrel_imm.
No functionality change.

llvm-svn: 181153
2013-05-05 13:29:02 +00:00
Richard Osborne
6600501755 [XCore] Add BLRB instructions.
llvm-svn: 181152
2013-05-05 13:24:16 +00:00