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244 Commits

Author SHA1 Message Date
Tom Stellard
3a335f24af R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
 2013-05-06 23:02:19 +00:00
Tom Stellard
57e8e4e921 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181268
 2013-05-06 23:02:15 +00:00
Tom Stellard
d2ec929c52 R600/SI: Add intrinsic for texture image loading 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
 2013-05-06 23:02:12 +00:00
Tom Stellard
4ed2501894 R600/SI: Add pattern for uint_to_fp 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181266
 2013-05-06 23:02:07 +00:00
Tom Stellard
7d53018f9b R600/SI: Add patterns for integer maxima / minima 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181265
 2013-05-06 23:02:04 +00:00
Tom Stellard
2c5ed6e6ce R600/SI: Add pattern for AMDGPU.trunc intrinsic 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181263
 2013-05-06 23:02:00 +00:00
Tom Stellard
740d847e2c R600: Remove dead code from the CodeEmitter v2 
v2:
  - Replace switch statement with TSFlags query

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181229
 2013-05-06 17:50:57 +00:00
Tom Stellard
fb8e73f3af R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
 2013-05-06 17:50:51 +00:00
Tom Stellard
6c3f6e1b02 R600: Stop emitting the instruction type byte before each instruction 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
 2013-05-06 17:50:44 +00:00
Tom Stellard
ebe049fd75 R600: Emit ISA for CALL_FS_* instructions 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
 2013-05-06 17:50:26 +00:00
Tom Stellard
2165728987 R600: Expand vector or, shl, srl, and xor nodes 
llvm-svn: 181035
 2013-05-03 17:21:31 +00:00
Tom Stellard
9015d64c2e R600: BFI_INT is a vector-only instruction 
llvm-svn: 181034
 2013-05-03 17:21:24 +00:00
Tom Stellard
f2fd0109a0 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

llvm-svn: 181033
 2013-05-03 17:21:20 +00:00
Tom Stellard
00f307d8e4 R600: Clean up comments in Processors.td 
llvm-svn: 181032
 2013-05-03 17:21:14 +00:00
Vincent Lejeune
5d7b2a4aea R600: Signed literals are 64bits wide 
llvm-svn: 180960
 2013-05-02 21:53:03 +00:00
Vincent Lejeune
3ff31b75b3 R600: If previous bundle is dot4, PV valid chan is always X 
llvm-svn: 180959
 2013-05-02 21:52:55 +00:00
Vincent Lejeune
33415b0699 R600: Improve asmPrint of ALU clause 
llvm-svn: 180957
 2013-05-02 21:52:40 +00:00
Vincent Lejeune
62da1453e1 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Tom Stellard
6f9f86852b R600: Use new tablegen syntax for patterns 
All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

llvm-svn: 180922
 2013-05-02 15:30:12 +00:00
Tom Stellard
ccaeffd7d5 R600/SI: remove nonsense select pattern 
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>
llvm-svn: 180921
 2013-05-02 15:30:07 +00:00
Vincent Lejeune
8054d1e2f8 R600: Always use texture cache for compute shaders 
This will improve the performance of memory reads.

llvm-svn: 180762
 2013-04-30 00:14:44 +00:00
Vincent Lejeune
29f24e0ce8 R600: use native for alu 
llvm-svn: 180761
 2013-04-30 00:14:38 +00:00
Vincent Lejeune
c6ba980992 R600: Packetize instructions 
llvm-svn: 180760
 2013-04-30 00:14:27 +00:00
Vincent Lejeune
176c8200bc R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 
llvm-svn: 180759
 2013-04-30 00:14:17 +00:00
Vincent Lejeune
7878fed9de R600: Add a Bank Swizzle operand 
llvm-svn: 180758
 2013-04-30 00:14:08 +00:00
Vincent Lejeune
b2f40c2a8c R600: Take inner dependency into tex/vtx clauses 
llvm-svn: 180757
 2013-04-30 00:14:00 +00:00
Vincent Lejeune
4d300cefe8 R600: Turn TEX/VTX into native instructions 
llvm-svn: 180756
 2013-04-30 00:13:53 +00:00
Vincent Lejeune
e641cd06c9 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755
 2013-04-30 00:13:39 +00:00
Vincent Lejeune
1b276d48e1 R600: Add some new processor variants 
llvm-svn: 180753
 2013-04-30 00:13:27 +00:00
Vincent Lejeune
fabf120f32 R600: Clean up instruction class definitions 
llvm-svn: 180752
 2013-04-30 00:13:20 +00:00
Vincent Lejeune
f8d86cf88b R600: config section now reports use of killgt 
llvm-svn: 180751
 2013-04-30 00:13:13 +00:00
Tom Stellard
33e7a52e1c R600: Use correct CF_END instruction on Northern Island GPUs 
llvm-svn: 180735
 2013-04-29 22:23:58 +00:00
Tom Stellard
a22d2b47f3 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

llvm-svn: 180734
 2013-04-29 22:23:54 +00:00
Tom Stellard
de2ad0a8f1 R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 180620
 2013-04-26 18:32:24 +00:00
Tom Stellard
222f7ab2fb R600: Initialize BooleanVectorContents 
Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231
 2013-04-24 23:56:18 +00:00
Tom Stellard
48d161332e R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
3666f07489 R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
e5ba5f1b14 R600: Add CF_END 
llvm-svn: 180123
 2013-04-23 17:34:00 +00:00
Matt Arsenault
b7287bba9b Remove unused DwarfSectionOffsetDirective string 
The value isn't actually used, and setting it emits a COFF specific
directive.

llvm-svn: 180064
 2013-04-22 22:49:11 +00:00
Michael Liao
3b258b6b24 ArrayRefize getMachineNode(). No functionality change. 
llvm-svn: 179901
 2013-04-19 22:22:57 +00:00
Tom Stellard
017c53ebbd R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard
db47653487 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829
 2013-04-19 02:11:00 +00:00
Vincent Lejeune
cd0483fb18 R600: Make Export Instruction not duplicable 
llvm-svn: 179686
 2013-04-17 15:17:39 +00:00
Vincent Lejeune
a1a9b1752d R600: Export is emitted as a CF_NATIVE inst 
llvm-svn: 179685
 2013-04-17 15:17:32 +00:00
Vincent Lejeune
966453087f R600: Emit used GPRs count 
llvm-svn: 179684
 2013-04-17 15:17:25 +00:00
Tom Stellard
bd67f8cd81 R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard
a44e2e18a1 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Tom Stellard
cb4468b00a R600: Emit ELF formatted code rather than raw ISA. 
llvm-svn: 179544
 2013-04-15 17:51:21 +00:00
NAKAMURA Takumi
c9309ae42b R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable] 
llvm-svn: 179263
 2013-04-11 04:16:27 +00:00
NAKAMURA Takumi
1837d9ec3e Whitespace. 
llvm-svn: 179262
 2013-04-11 04:16:22 +00:00