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969 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
008b36037d Remove the last mentions of sub_ss and sub_sd from patterns. 
I'll remove these two sub-register indexes shortly.

llvm-svn: 160831
 2012-07-26 23:03:08 +00:00
Jakob Stoklund Olesen
c1dd7a213d Eliminate sub_ss, sub_sd from broadcast patterns. 
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but
copyPhysReg does the right thing with it. (The old pattern would
eventually produce the same cross-class copy).

llvm-svn: 160830
 2012-07-26 22:59:06 +00:00
Jakob Stoklund Olesen
419ccae442 Eliminate more sub_ss / sub_sd patterns. 
This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns,
simplifying the emitted code a bit.

llvm-svn: 160820
 2012-07-26 22:30:18 +00:00
Jakob Stoklund Olesen
0a41a45c36 Eliminate some SUBREG_TO_REG patterns with sub_ss and sub_sd. 
The SUBREG_TO_REG instruction has magic semantics asserting that the
source value was defined by an instruction that cleared the high half of
the register. Those semantics are never actually exploited for xmm
registers.

llvm-svn: 160818
 2012-07-26 22:03:21 +00:00
Jakob Stoklund Olesen
44868927b9 Eliminate a batch of uses of sub_ss and sub_sd in the X86 target. 
These idempotent sub-register indices don't do anything --- They simply
map XMM registers to themselves.  They no longer affect register classes
either since the SubRegClasses field has been removed from Target.td.

This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns
with COPY_TO_REGCLASS patterns which simply become COPY instructions.

The number of IMPLICIT_DEF instructions before register allocation is
reduced, and that is the cause of the test case changes.

llvm-svn: 160816
 2012-07-26 21:40:42 +00:00
Craig Topper
9667d599eb Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. 
llvm-svn: 160775
 2012-07-26 07:48:28 +00:00
Nadav Rotem
03d2729392 The vbroadcast family of instructions has 'fallback patterns' in case where the 
load source operand is used by multiple nodes. The v2i64 broadcast was emulated
by shuffling the two lower i32 elements to the upper two.
We had a bug in the immediate used for the broadcast.
Replacing 0 to 0x44.
0x44 means [01|00|01|00] which corresponds to the correct lane.

Patch by Michael Kuperstein.

llvm-svn: 160430
 2012-07-18 08:14:48 +00:00
Craig Topper
b144f3b6db Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
llvm-svn: 160420
 2012-07-18 04:11:12 +00:00
Nadav Rotem
0377e0d234 Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention. 
Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot.

PR12782.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>

llvm-svn: 160230
 2012-07-15 12:26:30 +00:00
Craig Topper
a75da664ff Mark VINSERTI128rm as MayLoad=1. Fixes PR13348. 
llvm-svn: 160162
 2012-07-13 05:46:28 +00:00
Craig Topper
6eef81b65b Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren. 
llvm-svn: 160110
 2012-07-12 06:52:41 +00:00
Craig Topper
b346ce8240 Reverse assembler/disassembler operand order for gather instructions. 
llvm-svn: 159983
 2012-07-10 06:38:33 +00:00
Craig Topper
4644d3577c Remove extra space. 
llvm-svn: 159647
 2012-07-03 06:48:58 +00:00
Craig Topper
60bbc2fde8 Change i128mem/i256mem to f128mem/f256mem on some floating point vector instructions. 
llvm-svn: 159646
 2012-07-03 06:11:06 +00:00
Craig Topper
6fcb4454a0 Add aliases for pblendvb, blendvpd, and blendvps instructions with the implicit xmm0 operand specified. Fixes PR13252. 
llvm-svn: 159644
 2012-07-03 05:49:45 +00:00
Elena Demikhovsky
0617b5a56c Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2. 
llvm-svn: 159504
 2012-07-01 06:12:26 +00:00
Manman Ren
63bf58865a X86: add more GATHER intrinsics in LLVM 
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
  from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
  from 256-bit to 128-bit.

Support the following intrinsics:
  llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
  llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
  llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
  llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256

llvm-svn: 159402
 2012-06-29 00:54:20 +00:00
Manman Ren
6be46b7b4c X86: add GATHER intrinsics (AVX2) in LLVM 
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221
 2012-06-26 19:47:59 +00:00
Craig Topper
5c8bdeb3f3 Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead. 
llvm-svn: 159184
 2012-06-26 04:12:49 +00:00
Craig Topper
df4e56ebc1 Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because there are no patterns in the instruction. 
llvm-svn: 159127
 2012-06-25 06:51:42 +00:00
Craig Topper
2959047de1 Remove codegen only instruction in favor of one that has the same definition. Make some pattern operands more explicit about types. 
llvm-svn: 159126
 2012-06-25 06:16:00 +00:00
Craig Topper
3f09003ac6 Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
llvm-svn: 159109
 2012-06-24 07:07:16 +00:00
Craig Topper
bbce66a591 Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
llvm-svn: 159108
 2012-06-24 06:55:37 +00:00
Craig Topper
677692bc32 Fix build failures from r159106. 
llvm-svn: 159107
 2012-06-24 06:08:31 +00:00
Craig Topper
58ede28106 Remove intrinsic specific instructions for CVTPD2PS and replace with just patterns. 
llvm-svn: 159106
 2012-06-24 05:44:31 +00:00
Craig Topper
7485c05a49 Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns. 
llvm-svn: 159105
 2012-06-24 05:33:24 +00:00
Craig Topper
e824497e82 Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead instead. 
llvm-svn: 159090
 2012-06-23 22:33:14 +00:00
Craig Topper
59fcd68657 Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment. 
llvm-svn: 159087
 2012-06-23 20:52:45 +00:00
Craig Topper
caf5a8e7aa Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to the SSE2 section of the file. 
llvm-svn: 159086
 2012-06-23 20:15:42 +00:00
Craig Topper
7067c92fbb Use correct memory types for (V)CVTDQ2PD instructions. 
llvm-svn: 159075
 2012-06-23 08:30:27 +00:00
Craig Topper
b05bd41aed Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with intrinsic patterns. Mem forms omitted because the load size is only 64-bits. 
llvm-svn: 159070
 2012-06-23 04:23:36 +00:00
Craig Topper
f19d6cef51 Add predicate check around some patterns. 
llvm-svn: 158797
 2012-06-20 07:30:23 +00:00
Craig Topper
54d8fe551b Add predicate check around some patterns. 
llvm-svn: 158795
 2012-06-20 07:01:11 +00:00
Kay Tiong Khoo
7247ab8114 *no need to pollute Intel syntax with bonus mnemonics; operand size is explicitly specified 
llvm-svn: 158603
 2012-06-16 17:19:49 +00:00
Craig Topper
8d23b98818 Mark several instructions SSE2 instead of SSE3 as they should be. 
llvm-svn: 158049
 2012-06-06 06:45:27 +00:00
Benjamin Kramer
cb686400fb X86: Rename the CLMUL target feature to PCLMUL. 
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

llvm-svn: 157745
 2012-05-31 14:34:17 +00:00
Craig Topper
c6bd90e646 Add intrinsic for pclmulqdq instruction. 
llvm-svn: 157731
 2012-05-31 04:37:40 +00:00
Benjamin Kramer
0c823ae0ed Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Craig Topper
77b1a4cee5 Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit. 
llvm-svn: 156375
 2012-05-08 06:58:15 +00:00
Craig Topper
02644ca6b7 Fix some issues in the f16c instructions. 
llvm-svn: 156287
 2012-05-07 06:00:15 +00:00
Craig Topper
c6d0bc2afc Add SSE4A MOVNTSS/MOVNTSD instructions. 
llvm-svn: 156281
 2012-05-07 05:36:19 +00:00
Nadav Rotem
021d75713c AVX: Add additional vbroadcast replacement sequences for integers. 
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.

llvm-svn: 155461
 2012-04-24 18:09:59 +00:00
Nadav Rotem
d060c25823 AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions 
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).

llvm-svn: 155437
 2012-04-24 11:07:03 +00:00
Elena Demikhovsky
35721fc4f8 ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2 
llvm-svn: 155309
 2012-04-22 09:39:03 +00:00
Craig Topper
db4fcf7088 Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes. 
llvm-svn: 154801
 2012-04-16 07:13:00 +00:00
Craig Topper
129dccdc84 Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second. 
llvm-svn: 154797
 2012-04-16 06:26:15 +00:00
Craig Topper
1b15347812 Merge vpermps/vpermd and vpermpd/vpermq SD nodes. 
llvm-svn: 154782
 2012-04-16 00:41:45 +00:00
Craig Topper
788250eec1 Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors. 
llvm-svn: 154778
 2012-04-15 22:43:31 +00:00
Nadav Rotem
2a4e2ef10c Fix PR12529. The Vxx family of instructions are only supported by AVX. 
Use non-vex instructions for SSE4.

llvm-svn: 154770
 2012-04-15 19:36:44 +00:00
Elena Demikhovsky
92fb3e613e Added VPERM optimization for AVX2 shuffles 
llvm-svn: 154761
 2012-04-15 11:18:59 +00:00
Craig Topper
448790d566 Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. 
llvm-svn: 154580
 2012-04-12 07:23:00 +00:00
Nadav Rotem
c922b4f2a3 Reapply 154396 after fixing a test. 
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.

llvm-svn: 154483
 2012-04-11 06:40:27 +00:00
Eric Christopher
f8886e8f48 Temporarily revert this patch to see if it brings the buildbots back. 
llvm-svn: 154425
 2012-04-10 19:33:16 +00:00
Nadav Rotem
74f87a6bd8 Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. 
blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.

llvm-svn: 154396
 2012-04-10 14:33:13 +00:00
Craig Topper
a6412fb8c0 Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1. 
llvm-svn: 154272
 2012-04-07 22:32:29 +00:00
Craig Topper
1ddf62dc2c Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns. 
llvm-svn: 154268
 2012-04-07 21:57:43 +00:00
Craig Topper
ce6c05e0df Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
llvm-svn: 153935
 2012-04-03 05:20:24 +00:00
Chad Rosier
17f25ea47b [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to 
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570

llvm-svn: 153139
 2012-03-20 21:43:40 +00:00
Chad Rosier
f6d522341c [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give 
precedence over the VINSERTF128 avx1 patterns.

llvm-svn: 153114
 2012-03-20 19:45:07 +00:00
Chad Rosier
73d8191b27 Whitespace. 
llvm-svn: 153105
 2012-03-20 18:38:33 +00:00
Chad Rosier
ffd2dbd676 [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove 
whitespace from test case.  No functional change intended.

llvm-svn: 153103
 2012-03-20 18:24:55 +00:00
Chad Rosier
143f33dc92 [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. 
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953

llvm-svn: 153092
 2012-03-20 17:08:51 +00:00
Chad Rosier
bd3e55d39c [avx] Add patterns for VINSERTF128rm. 
This results in things such as

	vmovaps	-96(%rbx), %xmm1
	vinsertf128	$1, %xmm1, %ymm0, %ymm0

to be combined to
         
	vinsertf128	$1, -96(%rbx), %ymm0, %ymm0

rdar://10643481

llvm-svn: 152762
 2012-03-15 00:45:30 +00:00
Kay Tiong Khoo
aaa4140718 *fix typo in comment; test of commit access 
llvm-svn: 152507
 2012-03-10 21:29:49 +00:00
Chad Rosier
a10cf5e1b9 Fix a regression from r147481. 
Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078

llvm-svn: 152366
 2012-03-09 02:00:48 +00:00
Preston Gurd
e0609ed607 This patch adds instruction latencies for the SSE instructions 
to the instruction scheduler for the Intel Atom.

llvm-svn: 151590
 2012-02-27 23:35:03 +00:00
Pete Cooper
135769381b Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics 
llvm-svn: 151342
 2012-02-24 03:51:49 +00:00
Jia Liu
6bb2f0f0e4 some comment fix for X86 and ARM 
llvm-svn: 150902
 2012-02-19 02:03:36 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Craig Topper
a25b84d986 Remove the last of the old vector_shuffle patterns from X86 isel. 
llvm-svn: 150795
 2012-02-17 07:02:34 +00:00
Craig Topper
a754fb54b1 Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel. 
llvm-svn: 150462
 2012-02-14 08:14:53 +00:00
Craig Topper
f70ffc68b2 Still more vector_shuffle pattern removal. 
llvm-svn: 150365
 2012-02-13 07:23:41 +00:00
Craig Topper
3073033e59 Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel. 
llvm-svn: 150363
 2012-02-13 05:48:49 +00:00
Craig Topper
5cb2de69d8 Recommit r150328. Previous test failures should be fixed by r150360. 
llvm-svn: 150362
 2012-02-13 05:10:10 +00:00
NAKAMURA Takumi
50b0952aa9 Revert r150328, "Remove more vector_shuffle patterns." 
It caused 3 failures on pre-penryn and non-x86(generic) hosts.

llvm-svn: 150357
 2012-02-13 00:10:15 +00:00
Craig Topper
76547b82f2 Remove more vector_shuffle patterns. 
llvm-svn: 150328
 2012-02-12 08:14:35 +00:00
Craig Topper
96a1a31c5c Remove more vector_shuffle patterns. 
llvm-svn: 150321
 2012-02-12 01:07:34 +00:00
Craig Topper
7c85e63244 Remove more vector_shuffle patterns. 
llvm-svn: 150314
 2012-02-11 23:31:01 +00:00
Craig Topper
59398d7eb3 Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel. 
llvm-svn: 150299
 2012-02-11 07:43:35 +00:00
Craig Topper
f19c739d2d Remove a couple unneeded intrinsic patterns 
llvm-svn: 150067
 2012-02-08 08:29:30 +00:00
Craig Topper
6dbd5e534c Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
llvm-svn: 150060
 2012-02-08 06:36:57 +00:00
Craig Topper
a8a69356e1 Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
llvm-svn: 149968
 2012-02-07 06:28:42 +00:00
Craig Topper
07b9d056fa Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
llvm-svn: 149807
 2012-02-05 03:14:49 +00:00
Elena Demikhovsky
7ca11b6e3f Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.

llvm-svn: 149600
 2012-02-02 09:10:43 +00:00
Andrew Trick
d09b64fc25 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
Craig Topper
9a8c6c1633 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. 
llvm-svn: 149232
 2012-01-30 07:50:31 +00:00
Craig Topper
9259da4826 Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. 
llvm-svn: 149122
 2012-01-27 07:09:40 +00:00
Victor Umansky
bf35274368 Fix for the following bug in AVX codegen for double-to-int conversions: 
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 

llvm-svn: 149056
 2012-01-26 08:51:39 +00:00
Craig Topper
814a037ac6 Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM. 
llvm-svn: 149053
 2012-01-26 07:31:30 +00:00
Craig Topper
7ed643d290 Remove some more patterns by custom lowering intrinsics to target specific nodes. 
llvm-svn: 149052
 2012-01-26 07:18:03 +00:00
Craig Topper
c2b030401c Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
llvm-svn: 148933
 2012-01-25 06:43:11 +00:00
Craig Topper
9edaa5c15a Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
llvm-svn: 148927
 2012-01-25 05:37:32 +00:00
Craig Topper
c968a4ccc9 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
llvm-svn: 148922
 2012-01-25 04:42:03 +00:00
Craig Topper
f4166abe42 Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
llvm-svn: 148914
 2012-01-25 03:52:09 +00:00
Craig Topper
606872615f Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
llvm-svn: 148687
 2012-01-23 08:18:28 +00:00
Craig Topper
360c9f28cf Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
llvm-svn: 148684
 2012-01-23 06:16:53 +00:00
Craig Topper
03b49e88a2 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. 
llvm-svn: 148672
 2012-01-23 00:06:44 +00:00
Craig Topper
b80bb890b6 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
llvm-svn: 148670
 2012-01-22 23:36:02 +00:00
Craig Topper
558395cb4e Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
llvm-svn: 148667
 2012-01-22 22:42:16 +00:00
Craig Topper
2b6951f7c4 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
llvm-svn: 148664
 2012-01-22 19:15:14 +00:00