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Commit Graph

3065 Commits

Author SHA1 Message Date
Andrew Lenharth
cbf7a52768 WOW, function calls still seem to work after this.
llvm-svn: 21286
2005-04-13 17:17:28 +00:00
Andrew Lenharth
d1fee6d24a prepare for func call optimization
llvm-svn: 21285
2005-04-13 16:19:50 +00:00
Duraid Madina
b9d2d9ac63 * add the shladd instruction
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
2005-04-13 06:12:04 +00:00
Andrew Lenharth
ec33ab6a2f add matches for SxADDL and company, as well as simplify the SxADDQ code
llvm-svn: 21281
2005-04-13 05:19:55 +00:00
Duraid Madina
67e553e521 * if ANDing with a constant of the form:
0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279
2005-04-13 04:50:54 +00:00
Andrew Lenharth
510db15268 added all flavors of zap for anding
llvm-svn: 21276
2005-04-13 03:47:03 +00:00
Chris Lattner
85c6a7bed0 Fix some mysteriously missing {}'s which cause the miscompilation of
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
2005-04-13 03:29:53 +00:00
Chris Lattner
8489ac991d remove one more occurance of this that snuck in
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
Chris Lattner
5fdb103328 Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270
2005-04-13 02:43:40 +00:00
Chris Lattner
a2e92e69da Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269
2005-04-13 02:41:52 +00:00
Chris Lattner
26c7c9150a Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268
2005-04-13 02:40:26 +00:00
Chris Lattner
f25fefd9cf Z_E_I is gone
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
Nate Begeman
a56527ea5f Fold shift by size larger than type size to undef
Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261
2005-04-12 23:12:17 +00:00
Nate Begeman
79c8b8fd1c Implement setcc op, -1 sequences
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260
2005-04-12 21:22:28 +00:00
Duraid Madina
39fcec1541 * OK, after changing to use liveIn/liveOut instead of IDEFs,
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

llvm-svn: 21252
2005-04-12 18:42:59 +00:00
Andrew Lenharth
174d44f223 Get rid of idefs for arguments (oops)
llvm-svn: 21251
2005-04-12 17:47:57 +00:00
Andrew Lenharth
1b8a8331c9 Get rid of idefs for arguments
llvm-svn: 21250
2005-04-12 17:35:16 +00:00
Chris Lattner
be2dceff48 Put out* into the allocation order, allowing the register allocator to
coallesce moves into outgoing args.

llvm-svn: 21249
2005-04-12 15:12:51 +00:00
Chris Lattner
37712352c0 Make sure to realize that calls use their argument regs
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
Duraid Madina
2821f99f19 stop emitting IDEFs for args - change to using liveIn/liveOut
llvm-svn: 21247
2005-04-12 14:54:44 +00:00
Nate Begeman
f96b42f1b6 Initial support for allocation condition registers
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
Nate Begeman
a154deaaff Implement bitfield clears
Implement divide by negative power of two

llvm-svn: 21240
2005-04-12 00:10:02 +00:00
Nate Begeman
f31b58f145 Update PPC readme. Remove things that are done or aren't ppc specific
llvm-svn: 21232
2005-04-11 20:48:57 +00:00
Chris Lattner
55e620f08d IA64 supports this operation.
llvm-svn: 21228
2005-04-11 18:55:36 +00:00
Chris Lattner
ee715b2abc ORo sets CR0
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
Chris Lattner
7d11f40ee2 Revert the previous patch, which I didn't mean to check in.
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
Chris Lattner
d925c74452 Fix a minor bug (ORo didn't mark that it set CR0).
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225
2005-04-11 15:01:39 +00:00
Duraid Madina
01aaf77792 hmm, should probably change addImm() to take 64-bit arguments one day anyway.
llvm-svn: 21224
2005-04-11 07:16:39 +00:00
Nate Begeman
783fe2108e Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
(1.5%) instructions in 186.crafty

llvm-svn: 21222
2005-04-11 06:34:10 +00:00
Duraid Madina
d2ae9221c7 assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.

llvm-svn: 21221
2005-04-11 05:55:56 +00:00
Nate Begeman
34aa7ec9cb Fix another fixme: factor out the constant fp generation code.
llvm-svn: 21207
2005-04-10 06:06:10 +00:00
Nate Begeman
b6c9b326e3 Fix 64 bit argument loading that straddles the args in regs / args on stack
boundary.

llvm-svn: 21206
2005-04-10 05:53:14 +00:00
Nate Begeman
0a43e95718 Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
have to inform the register allocator it might be stepped on.

llvm-svn: 21202
2005-04-10 03:59:42 +00:00
Nate Begeman
f5cedbc812 Make sure that BRCOND branches can be converted into long branches too.
llvm-svn: 21198
2005-04-10 01:48:29 +00:00
Nate Begeman
ab8e705a52 Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
llvm-svn: 21197
2005-04-10 01:14:13 +00:00
Chris Lattner
c1bacbff9d rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
correct.  Remove the EmitComparison retvalue, as it is always the first arg.

Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty.  Crafty now works!

llvm-svn: 21195
2005-04-10 01:03:31 +00:00
Nate Begeman
a2374d39df fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
llvm-svn: 21193
2005-04-09 23:35:05 +00:00
Chris Lattner
17c60891c1 Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
This caused the "use before a def" assertion on some programs.

With this patch, 254.gap now passes with the PPC backend.

llvm-svn: 21191
2005-04-09 22:05:17 +00:00
Chris Lattner
b630949c2e do not set the root to null if an argument is dead
llvm-svn: 21188
2005-04-09 21:23:24 +00:00
Nate Begeman
dda6155d19 Add rlwnm instruction for variable rotate
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality

llvm-svn: 21187
2005-04-09 20:09:12 +00:00
Chris Lattner
72b1964108 Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
llvm-svn: 21185
2005-04-09 19:47:21 +00:00
Chris Lattner
c97f9f403f Switch this instruction selector over to using liveins and liveouts, eliminating
implicit defs on entry to the function.  yaay :)

llvm-svn: 21184
2005-04-09 16:32:30 +00:00
Chris Lattner
fd4d6e0847 Use live out sets for return values instead of imp_defs, which is cleaner and faster.
llvm-svn: 21181
2005-04-09 15:23:56 +00:00
Duraid Madina
2d3e52576d ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
* fix overallocation of integer (stacked) registers: we can't allocate
  registers for local use if they are required as output registers

this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.

llvm-svn: 21178
2005-04-09 11:53:00 +00:00
Nate Begeman
98bcb13bfa Optimize FSEL a bit for fneg arguments. This fixes the recently added test
case so that we emit

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fsel f1, f1, f3, f2
        blr

instead of:

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fneg f0, f1
        fneg f0, f0
        fsel f1, f0, f3, f2
        blr

llvm-svn: 21177
2005-04-09 09:33:07 +00:00
Chris Lattner
3fde68ea7a Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program
lets hope this doesn't break other programs with induced entropy

llvm-svn: 21174
2005-04-09 06:27:14 +00:00
Chris Lattner
39f963f968 This target does not support/want ISD::BRCONDTWOWAY
llvm-svn: 21164
2005-04-09 03:22:37 +00:00
Chris Lattner
c80baf5567 This target does not yet support ISD::BRCONDTWOWAY
llvm-svn: 21163
2005-04-09 03:22:30 +00:00
Nate Begeman
99fb6814bd 64b: Expand S/UREM
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
     Pattern match fsub a, mul(b, c) as fnmsub
     Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%

llvm-svn: 21161
2005-04-09 03:05:51 +00:00
Nate Begeman
95e1b860a1 Fix 64b shifts
llvm-svn: 21159
2005-04-08 23:45:01 +00:00